GENERAL DESCRIPTION
The MC68HC05J5A is a member of the low-cost high-performance M68HC05
Family of 8-bit microcontroller units (MCUs). The M68HC05 Family is based on
the customer-specified integrated circuit design strategy. All MCUs in the family
use the popular M68HC05 central processing unit (CPU) and are available with a
variety of subsystems, memory sizes and types, and package types.
The MC68HC05J5A is an enhanced version of the MC68HC05J5, with expanded
RAM, ROM sizes, and an additional 16-bit timer with TCAP. This MCU is available
in 20-pin PDIP, 20-pin SOIC, 16-pin PDIP, and 16-pin SOIC packages. The 16-pin
version has four less I/O lines.
Three variation on the MC68HC05J5A device are available; a summary of their
differences are listed in the following table:

FEATURES
The features of the MC68HC05J5A include the following:
• Industry standard M68HC05 CPU core
• Fully static operation with no minimum clock speed
• Power-saving STOP and WAIT modes
• Memory-Mapped Input/Output (I/O) registers
• 2560 Bytes of user ROM with security feature
• 128 Bytes of user RAM
• On-Chip Oscillator:
– Crystal/Resonator oscillator
– External clock oscillator
• 15-Bit Multi-function Timer
• 16-Bit Programmable Timer with Input Capture
• 14 Bidirectional I/O pins (10 I/O pins on 16-pin package)
– PA0-PA5, PB0, and PB3-PB5: with software programmable input pulldown
devices
– PB1, PB2, PA6 and PA7: open-drained I/O pins with software
programmable pull-up devices
– PA6, PA7, and PB1: with slow output falling transition feature
– PA7: with falling-edge interrupt capability
– PA0-PA3: with maskable rising-edge only or rising-edge and high
level interrupt capability
– 20-pin package: PB1 and PB2, each with 25mA current sink
capability
– 16-pin package: PB1 with 50mA current sink capability
• Computer Operation Properly (COP) Watchdog
• Low Voltage Reset Circuit
• Illegal Address Reset
• 20-pin PDIP, 20-pin SOIC, 16-pin PDIP, and 16-pin SOIC packages