Description
The 5V49EE502 is a programmable clock generator
intended for high performance data-communications,
telecommunications, consumer, and networking
applications. There are four internal PLLs, each individually
programmable, allowing for four unique non-integer-related
frequencies. The frequencies are generated from a single
reference clock. The reference clock can come from one of
the two redundant clock inputs. Automatic or manual
switchover function allows any one of the redundant clocks
to be selected during normal operation.
The 5V49EE502 is in-system, programmable and can be
programmed through the use of I2C interface. An internal
EEPROM allows the user to save and restore the
configuration of the device without having to reprogram it
on power-up.
Each of the four PLLs has an 7-bit reference divider and a
12-bit feedback divider. This allows the user to generate
four unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the
PLL response to the application. For instance, the user can
tune the PLL parameters to minimize jitter generation or to
maximize jitter attenuation. Spread spectrum generation
and/or fractional divides are allowed on two of the PLLs.
There are a total of four 8-bit output dividers. Each output
bank can be configured to support LVTTL, LVPECL, LVDS
or HCSL logic levels. Out0 (Output 0) supports 3.3V
single-ended standard only. The outputs are connected to
the PLLs via a switch matrix. The switch matrix allows the
user to route the PLL outputs to any output bank. This
feature can be used to simplify and optimize the board
layout. In addition, each output's slew rate and
enable/disable function is programmable.

Features
• Four internal PLLs
• Internal non-volatile EEPROM
• Fast (400kHz) mode I2C serial interface
• Input frequency range: 1MHz to 200MHz
• Output frequency range: 4.9kHz to 500MHz
• Reference crystal input with programmable linear load
capacitance
— Crystal frequency range: 8MHz to 50MHz
• Two independently controlled VDDO (1.8V to 3.3V)
• Each PLL has a 7-bit reference divider and a 12-bit
feedback-divider
• 8-bit output-divider blocks
• Fractional division capability on one PLL
• Two of the PLLs support spread spectrum generation
capability
• I/O standards:
— Outputs: 1.8V to 3.3 V LVTTL/ LVCMOS
— Outputs: LVPECL, LVDS and HCSL
— Inputs: 3.3 V LVTTL/ LVCMOS
• Programmable slew rate control
• Programmable loop bandwidth
• Programmable output inversion to reduce bimodal jitter
• Redundant clock inputs with auto and manual switchover
options
• Individual output enable/disable
• Power-down mode
• 3.3V core VDD
• Available in 24-QFN package
• -40° to +85°C industrial temperature operation