Features
• 2:1 LVDS MUX
• One LVDS output pair
• Two differential clock inputs can accept: LVPECL, LVDS, CML
• Maximum input/output frequency: 2.5GHz
• Translates LVCMOS/LVTTL input signals to LVDS levels by using
a resistor bias network on nPCLK0, nPCLK1
• RMS additive phase jitter: 0.06ps (typical)
• Propagation delay: 600ps (maximum)
• Part-to-part skew: 350ps (maximum)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Supports case temperature up to +105°C
• Available in lead-free (RoHS 6) package