1. General description
The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP),
set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that
meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored
in the flip-flop and appear at the nQ output. Inputs include clamp diodes. This enables the use of
current limiting resistors to interface inputs to voltages in excess VCC.
2. Features and benefits
• Wide supply voltage range from 1.0 V to 5.5 V
• Optimized for low voltage applications from 1.0 V to 3.6 V
• CMOS low power dissipation
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Direct interface with TTL levels (2.7 V to 3.6 V)
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C