1 Features
• Integrated BAW resonator, no need for external
reference
• Flexible frequency generation:
– Two channel dividers: up to three unique output
frequencies from 2.5 MHz to 400 MHz
– LVCMOS outputs supported up to 200 MHz: 1.8
V, 2.5 V, or 3.3 V
– Combination of AC-LVDS, DC-LVDS, LP-HCSL,
and LVCMOS on OUT0 and OUT1 pins
– Additional LVCMOS output for generation of up
to 5 LVCMOS clocks
• Total output frequency stability: ±25 ppm
• 2 functional modes: I2C or preprogrammed OTP
– Fully configurable I2C address
• Ambient temperature: –40 °C to 85 °C
• PCIe Gen 1 to Gen 6 compliant: Common Clock
with or without SSC, SRNS, and SRIS
• Very low PCIe jitter
– PCIe Gen 3 Common Clock jitter: 140 fs
maximum (PCIe limit is 1 ps)
– PCIe Gen 4 Common Clock jitter: 140 fs
maximum (PCIe limit is 500 fs)
– PCIe Gen 5 Common Clock jitter: 45 fs
maximum (PCIe limit is 150 fs)
– PCIe Gen 6 Common Clock jitter: 45 fs
maximum (PCIe limit is 100 fs)
• Mixed SSC and non-SSC output modes
supported, all PCIe Gen 1 to Gen 6 compliant
– 2x SSC outputs, 2x non-SSC outputs, or 1x
SSC output and 1x non-SSC output
• Programmable SSC modulation depth
– Preprogrammed: –0.1%, –0.25%, –0.3%, and –
0.5% down spread
– Register programmable: –0.1% to –3% down
spread or ±0.05% to ±1.5% center spread
• VDD = VDDO = 1.8 V / 2.5 V / 3.3 V ± 5%
• As low as 60 mA current consumption when both
outputs are LP-HCSL
• Internal LDOs with –93.1 dBc PSNR at 500 kHz
switching noise for LP-HCSL outputs
• Start-up time: <5 ms
• Output-to-output skew: <50 ps
• Fail-safe input and VDD pins

2 Applications
• PCIe Gen 1 to Gen 6 clock generation
• Server Motherboard
• NIC, SmartNIC
• Hardware Accelerator
• PCIe SSD
• Add-In Card, PCIe Expansion Card
• Multifunction Printer

3 Description
The LMK3H0102 is a 2-output PCIe Gen 1 to
Gen 6 compliant reference-less clock generator
with Spread Spectrum Clocking (SSC) support.
The part is based on TI proprietary Bulk Acoustic
Wave (BAW) technology and provides ±25-ppm
clock outputs without any crystal or external clock
reference. The device can provide two SSC clocks,
two non-SSC clocks, or one SSC clock and one
non-SSC clock at the same time. The device
meets the full PCIe compliance from Gen 1 to
Gen 6, including Common Clock with or without
SSC, Separate Reference No Spread (SNRS), and
Separate Reference Independent Spread (SRIS).
The device can be easily configured through either
GPIO pins or I2C interface. An external DC/DC can
be used to power the device. Refer to Power Supply
Recommendations for detailed guidelines on power
supply filtering and sourcing from DC/DC.