1 Features
• Vendor item drawing available, VID
V62/23627-01XE
• Total ionizing dose characterized at 30 krad (Si)
– Total ionizing dose radiation lot acceptance
testing (TID RLAT) for every wafer lot to 30
krad (Si)
• Single-event effects (SEE) characterized:
– Single event latch-up (SEL) immune to linear
energy transfer (LET) = 43 MeV-cm2 /mg
– Single event transient (SET) characterized to
43 MeV-cm2 /mg
• Wide operating range of 1.2 V to 5.5 V
• Single-supply translating gates at 5/3.3/2.5/1.8/1.2
V VCC
– TTL compatible inputs:
• Up translation:
– 1.8-V – Inputs from 1.2 V
– 2.5-V – Inputs from 1.8 V
– 3.3-V – Inputs from 1.8 V, 2.5 V
– 5.0-V – Inputs from 2.5 V, 3.3 V
• Down translation:
– 1.2-V – Inputs from 1.8 V, 2.5 V, 3.3 V,
5.0 V
– 1.8-V – Inputs from 2.5 V, 3.3 V, 5.0 V
– 2.5-V – Inputs from 3.3 V, 5.0 V
– 3.3-V – Inputs from 5.0 V
• 5.5 V tolerant input pins
• Output drive up to 25 mA AT 5-V
• Latch-up performance exceeds 250 mA per
JESD 17
• Space enhanced plastic (SEP)
– Controlled baseline
– Gold bondwire
– NiPdAu lead finish
– One assembly and test site
– One fabrication site
– Military (–55°C to 125°C) temperature range
– Extended product life cycle
– Product traceability
– Meets NASAs ASTM E595 outgassing
specification

2 Applications
• Enable or disable a digital signal
• Controlling an indicator LED
• Translation between communication modules and
system controllers

3 Description
The SN54SC4T00-SEP contains four independent 2-
input NAND Gates with Schmitt-trigger inputs. Each
gate performs the Boolean function Y = A ● B in
positive logic. The output level is referenced to the
supply voltage (VCC) and supports 1.8-V, 2.5-V, 3.3-V,
and 5-V CMOS levels.
The input is designed with a lower threshold circuit to
support up translation for lower voltage CMOS inputs
(for example 1.2 V input to 1.8 V output or 1.8 V input
to 3.3 V output). Additionally, the 5-V tolerant input
pins enable down translation (for example 3.3 V to 2.5
V output).