▪ Supports high-speed, low phase noise converter clocks
▪ Distribution, fanout, phase-delay of clock and SYSREF signals
▪ Very low output noise floor: -158.8dBc/Hz noise floor
(245.76MHz)
▪ Supports clock frequencies up to 3GHz, including clock output
frequencies of 983.04MHz, 491.52MHz, 245.76MHz, and
122.88MHz
▪ 4 output channels with a total of 16 differential outputs,
organized in:
• 8 dedicated clock outputs
• 8 outputs configurable as SYSREF outputs with individual
phase delay stages, or configurable as additional clock
outputs
▪ Each channel contains:
• Frequency dividers: ÷1, ÷2, ÷4, ÷6, ÷8, ÷12, ÷16
• Clock phase delay circuits
▪ Clock phase delay circuits
• Clock: delay unit is the clock period; 256 steps
• SYSREF: Configurable precision phase delay circuits:
8 steps of 131ps, 262ps, 393ps, or 524ps
▪ Flexible differential outputs:
• LVDS/LVPECL configurable
• Amplitude configurable
• Power-down modes for unused outputs
• Supports DC and AC coupling
• QREF (SYSREF) output pre-bias feature to prevent glitches
when turning output on or off
▪ Supply voltage:
• 3.3V core and signal I/O
• 1.8V Digital control SPI I/O (3.3V-tolerant inputs)
▪ 64 VFQFPN package (9 × 9 × 0.85 mm)
▪ Ambient temperature range: -40°C to +85°C