■ DESCRIPTION
The Fujitsu MB15F72SP is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1300 MHz and a 350 MHz prescalers. A 64/65 or a 128/129 for the 1300 MHz prescaler, and a 8/9 or a 16/17 for the 350 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.
MB15F72SP has the same configuration with MB15F02 or MB15F02L. The BiCMOS process is used , as a result a supply current is typically 2.7 mA typ. at 2.7 V.The supply voltage range is from 2.4 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial data.
The new package(BCC20) decreases a area of MB15F72SP more than 30 % comparing with the former BCC16 (for dual PLL).
MB15F72SP is ideally suited for wireless mobile communications, such as PDC

■ FEATURES
• High frequency operation:RF synthesizer: 1300 MHz max :IF synthesizer: 350 MHz max
• Low power supply voltage: VCC = 2.4 to 3.6 V
• Ultra Low power supply current:ICC = 2.7 mA typ. (VCC = Vp = 2.7 V, SWIF = SWRF = 0, Ta = +25°C, in IF, RF locking state)
• Direct power saving function:Power supply current in power saving mode Typ. 0.1 µA (VCC = Vp = 2.7 V, Ta = +25°C) Max. 10 µA (VCC = Vp = 2.7 V)
• Software selectable charge pump current: 1.5 mA/6.0 mA (typ.)
• Dual modulus prescaler: 1300 MHz prescaler (64/65 or 128/129 )/350 MHz prescaler (8/9 or 16/17)
• 23 bit shift resister
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
    - Binary 7-bit swallow counter: 0 to 127
    - Binary 11-bit programmable counter: 3 to 2,047
• On–chip phase control for phase comparator
• Built-in digital locking detector circuit to detect PLL locking and unlocking.
• Operating temperature: Ta = –40°C to +85°C
• Sireal data format compatible with MB15F02SL
• Small package BCC20 (3.4 mm × 3.6mm × 0.8mm)