Description
The ispLSI 1016E is a High Density Programmable Logic Device containing 96 Registers, 32 Universal I/O pins, four Dedicated Input pins, three Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1016E offers 5V non-volatile in-system programmability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the ispLSI 1016 architecture, the ispLSI 1016E device adds a new global output enable pin.

Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
    — 2000 PLD Gates
    — 32 I/O Pins, Four Dedicated Inputs
    — 96 Registers
    — High-Speed Global Interconnect
    — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
    — Small Logic Block Size for Random Logic
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
    — fmax = 125 MHz Maximum Operating Frequency
    — tpd = 7.5 ns Propagation Delay
    — TTL Compatible Inputs and Outputs
    — Electrically Erasable and Reprogrammable
    — Non-Volatile
    — 100% Tested at Time of Manufacture
    — Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
    — In-System Programmable (ISP™) 5V Only
    — Increased Manufacturing Yields, Reduced Time-to-Market and Improved Product Quality
    — Reprogram Soldered Device for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
    — Complete Programmable Device Can Combine Glue Logic and Structured Designs
    — Enhanced Pin Locking Capability
    — Three Dedicated Clock Input Pins
    — Synchronous and Asynchronous Clocks
    — Programmable Output Slew Rate Control to Minimize Switching Noise
    — Flexible Pin Placement
    — Optimized Global Routing Pool Provides Global Interconnectivity
    — Lead-Free Package Options