CS5460A datasheet(35/54 Pages) CIRRUS

35 / 54 page

CS5460A

Note also that in addition to the time-constants of

the input R-C filters, the phase-shifting properties

of the voltage/current sensors devices may also

contribute to the overall time-constants of the volt-

age/current input sensor networks. For example,

current-sense transformers and potential trans-

formers can impose phase-shifts on the sensed

current/voltage waveforms. Therefore, this possi-

ble source of additional phase-shift caused by sen-

sor devices may also need to be considered while

selecting the final R and C values for the volt-

age/current anti-aliasing filters. As an alternative

to, or in addition to the fine adjustment of the R and

C values of the two anti-alias filters, the CS5460A’s

phase compensation bits (see

Phase Compensa-

tion) can also be adjusted, in order to more closely

match the overall time-constants of the volt-

age/current input networks. Regardless of whether

the phase compensation bits are or are not used to

help more closely match the time-constants, this

requirement of equal time-constants must ulti-

mately be considered when selecting the final R

and C values that will be used for the input filters.

(Of course, this factor may not turn out to be so im-

portant if the designer is confident that the

mis-match between the voltage/current channel

time-constants will not cause enough error to vio-

late the accuracy requirements for the given pow-

er/energy metering application.)

3. Referring to the specs in

Section 1, note that the

differential input impedance across the current

channel input pins is only 30 k

Ω, which is signifi-

cantly less than the corresponding impedance

across the voltage channel input pins (which is

Ω). While the impedance across the voltage

channel is usually high enough to be ignored, the

impedance across the current channel inputs may

need to be taken into account by the designer

when the desired cutoff frequencies of the filters

(and the time-constants of the overall input net-

works) are computed. Also, because of this rather

low input impedance across the current channel in-

puts, the designer should note that as the values

for RI+ and/or RI- are increased, the interaction of

the current channel’s input impedance can begin to

cause a significant voltage drop within the current

channel input network. If this is not taken into ac-

count, values may be chosen for RI+ =RI- that are

large enough to cause a discrepancy between the

expected (theoretical) sensor gain and the

actual

sensor gain of the current sensor network, which

may not be anticipated by the designer. Also, if this

voltage drop effect is not considered, the designer

may select values for RI+ and RI that are slightly

larger than they should be, in terms of maximizing

the available dynamic range of the current channel

input. For the very same reason, the line-cur-

rent-to-sensor-output-voltage conversion factor of

the current sensor may not be optimized if this volt-

age division is not considered, when (for example)

selecting a value for the burden resistor for a given

current transformer. This issue should be consid-

ered, although a slight voltage drop only causes a

slight loss in available dynamic range, and the ef-

fects of this voltage drop on the actual current

channel sensor gain can be removed during gain

calibration of the current channel.

4. Referring to Figures 6 - 9, not all of the capaci-

tors/resistors shown in these example circuit dia-

grams are necessary; however, note that the all of

the filter capacitors (CV+, CV-, CI+, CI-, CVdiff, and CI-

diff

) can, in some situations, help to improve the

ability of both input networks to attenuate very

high-frequency RFI that can enter into the

CS5460A’s analog input pins. Therefore, during

layout of the PCB, these capacitors should be

placed in close proximity to their respective input

pins.

If any/all of the common-mode connected capaci-

tors (CV+, CV-, CI+, CI-) are included in the input net-

works, their values should be selected such that

they are at least one order of magnitude

smaller

than the value of the differential capacitors (CVdiff,

and CIdiff). This is done for at least two reasons:

a) The value tolerance for most types of commer-

cially available surface-mount capacitors is not

small enough to insure appreciable value match-

ing, between the value of CV+ vs. CV-, as well as

between the value of CV+ vs. CV-. Such value mis-

match can adversely affect the desired differen-

tial-mode response of the voltage/current input

networks. By keeping the values of these com-

mon-mode capacitors small, and allowing the val-

ue of the CVdiff, and CIdiff to dominate the

differential 1st-order time-constant of the input filter

networks, this undesirable possibility of frequency

response variation can be minimized.

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