CY29773AI datasheet(7/12 Pages) CYPRESS

7 / 12 page

CY29773

Document #: 38-07573 Rev. **

Page 7 of 12

tsk(O)

Output-to-Output Skew

Skew within Bank A

–

Skew within Bank B

–

100

Skew within Bank C

–

150

tsk(B)

Bank-to-Bank Skew

–

400

tPLZ, HZ

Output Disable Time

–

tPZL, ZH

Output Enable Time

–

PLL Closed Loop Bandwidth (-3dB)

÷4 Feedback

–

1.3 - 2.0

–

MHz

÷6 Feedback

–

0.7 - 1.3

–

÷8 Feedback

–

0.9 - 1.3

–

÷10 Feedback

–

0.6 - 1.1

–

÷12 Feedback

–

0.6 - 0.9

–

÷16 Feedback

–

0.4 - 0.6

–

÷20 Feedback

–

0.6 - 0.9

–

tJIT(CC)

Cycle-to-Cycle Jitter

Same frequency (125 MHz)

RMS (1

σ)

–7

Same frequency

–

150

Multiple frequencies

–

435

tJIT(PER)

Period Jitter

Same frequency (125 MHz)

RMS (1

σ)

–6

Same frequency

–

Multiple frequencies

–

235

tJIT(φ)

I/O Phase Jitter

–

150

tLOCK

Maximum PLL Lock Time

–

AC Electrical Specifications (VDD = 3.3V ±5%, TA = –40°C to +85°C)

[7]

Parameter

Description

Condition

Min.

Typ.

Max.

Unit

fVCO

VCO Frequency

200

–

500

MHz

fin

Input Frequency

÷4 Feedback

–

125

MHz

÷6 Feedback

33.3

–

83.3

÷8 Feedback

–

62.5

÷10 Feedback

–

÷12 Feedback

16.6

–

41.6

÷16 Feedback

12.5

–

31.25

÷20 Feedback

–

÷24 Feedback

8.3

–

20.8

÷32 Feedback

6.25

–

15.625

÷40 Feedback

–

12.5

Bypass mode (PLL_EN = 0)

–

200

frefDC

Input Duty Cycle

–

VPP

Peak-Peak Input Voltage

LVPECL

500

–

1000

VCMR

Common Mode Range[8]

LVPECL

1.2

–

VDD–0.9

tr , tf

TCLK Input Rise/FallTime

0.8V to 2.0V

–

1.0

AC Electrical Specifications (VDD = 2.5V ±5%, TA = –40°C to +85°C)

[7]

Parameter

Description

Condition

Min.

Typ.

Max.

Unit

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