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CY29773
Document #: 38-07573 Rev. **
Page 3 of 12
Table 1. Frequency Table
Feedback Output
Divider
VCO
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
(AVDD = 2.5V)
÷4
Input Clock * 4
50 MHz to 125 MHz
50 MHz to 95 MHz
÷6
Input Clock * 6
33.3 MHz to 83.3 MHz
33.3 MHz to 63.3 MHz
÷8.
Input Clock * 8
25 MHz to 62.5 MHz
25 MHz to 47.5 MHz
÷10
Input Clock * 10
20 MHz to 50 MHz
20 MHz to 38 MHz
÷12
Input Clock * 12
16.6 MHz to 41.6 MHz
16.6 MHz to 31.6 MHz
÷16
Input Clock * 16
12.5 MHz to 31.25 MHz
12.5 MHz to 23.75 MHz
÷20
Input Clock * 20
10 MHz to 25 MHz
10 MHz to19 MHz
÷24
Input Clock * 24
8.3 MHz to 20.8 MHz
8.3 MHz to 15.8 MHz
÷32
Input Clock * 32
6.25 MHz to 15.625 MHz
6.25 MHz to 11.8 MHz
÷40
Input Clock * 40
5 MHz to 12.5 MHz
5 MHz to 9.5 MHz
Table 2. Function Table (Configuration Controls)
Control
Default
0
1
REF_SEL
1
TCLK0, TCLK1
PECL_CLK
TCLK_SEL
1
TCLK0
TCLK1
VCO_SEL
1
VCO
÷2 (low input frequency range)
VCO
÷1 (high input frequency range)
PLL_EN
1
Bypass mode, PLL disabled. The input clock connects to the
output dividers
PLL enabled. The VCO output
connects to the output dividers
INV_CLK
1
QC2 and QC3 are in phase with QC0 and QC1
QC2 and QC3 are inverted (180° phase
shift) with respect to QC0 and QC1
MR#/OE
1
Outputs disabled (three-state) and reset of the device. During
reset/output disable the PLL feedback loop is open and the VCO
running at its minimum frequency. The device is reset by the
internal power-on reset (POR) circuitry during power-up.
Outputs enabled
Table 3. Function Table (Bank A)
VCO_SEL
SELA1
SELA0
QA(0:3)
00
0
÷8
00
1
÷12
01
0
÷16
01
1
÷24
10
0
÷4
10
1
÷6
11
0
÷8
11
1
÷12
Table 4. Function Table (Bank B)
VCO_SEL
SELB1
SELB0
QB(0:3)
00
0
÷8
00
1
÷12
01
0
÷16
01
1
÷20
10
0
÷4
10
1
÷6
11
0
÷8
11
1
÷10
Table 5. Function Table (Bank C)
VCO_SEL
SELC1
SELC0
QC(0:3)
00
0
÷4
00
1
÷8
01
0
÷12
01
1
³16
10
0
÷2
10
1
÷4
11
0
÷6
11
1
÷8
Table 6. Function Table (FB_OUT)
VCO_SEL
FB_SEL2
FB_SEL1
FB_SEL0
FB_OUT
0
000
÷8
0
001
÷12
0
010
÷16
0
011
÷20
0
100
÷16
0
101
÷24
0
110
÷32
0
111
÷40
1
000
÷4
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