HT36A2 datasheet(10/24 Pages) HOLTEK

10 / 24 page

HT36A2

Rev. 1.00

June 19, 2003

the interrupt request will not be acknowledged, even if

the related interrupt is enabled, until the SP is decre-

mented. If immediate service is desired, the stack must

be prevented from becoming full.

All these kinds of interrupt have a wake-up capability. As

an interrupt is serviced, a control transfer occurs by

pushing the program counter onto the stack and then

branching to subroutines at specified locations in the

program memory. Only the program counter is pushed

onto the stack. If the contents of the register and Status

program which may corrupt the desired control se-

quence, then the programmer must save the contents

first.

The internal Timer Counter 0 interrupt is initialized by

setting the Timer Counter 0 interrupt request flag (T0F;

bit 5 of INTC), caused by a Timer Counter 0 overflow.

When the interrupt is enabled, and the stack is not full

and the T0F bit is set, a subroutine call to location 08H

will occur. The related interrupt request flag (T0F) will be

reset and the EMI bit cleared to disable further inter-

rupts.

The Timer Counter 1 interrupt is operated in the same

manner as Timer Counter 0. The related interrupt con-

trol bits ET1I and T1F of the Timer Counter 1 are bit 3

and bit 6 of the INTC respectively.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are held until the RETI in-

struction is executed or the EMI bit and the related

interrupt control bit are set to 1 (if the stack is not full). To

return from the interrupt subroutine, the RET or RETI in-

struction may be invoked. RETI will set the EMI bit to en-

able an interrupt service, but RET will not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the priorities in the following table apply. These can be

masked by resetting the EMI bit.

Interrupt Source

Priority

Vector

Timer Counter 0 overflow

08H

Timer Counter 1 overflow

0CH

The Timer Counter 0/1 interrupt request flag (T0F/T1F),

Enable Timer Counter 0/1 bit (ET0I/ET1I) and Enable

Master Interrupt bit (EMI) constitute an interrupt control

ory. EMI, ET0I, ET1I are used to control the en-

abling/disabling of interrupts. These bits prevent the

requested interrupt from being serviced. Once the inter-

rupt request flags (T0F, T1F) are set, they will remain in

the INTC register until the interrupts are serviced or

cleared by a software instruction.

It is recommended that a program does not use the

²CALL subroutine² within the interrupt subroutine. Be-

cause interrupts often occur in an unpredictable manner

or need to be serviced immediately in some applica-

tions, if only one stack is left and enabling the interrupt is

not well controlled, once the

²CALL subroutine² operates

in the interrupt subroutine, it may damage the original

control sequence.

Oscillator Configuration

The HT36A2 provides two types of oscillator circuit for

the system clock, i.e., RC oscillator and crystal oscilla-

tor. No matter what type of oscillator, the signal divided

by 2 is used for the system clock. The HALT mode stops

the system oscillator and ignores external signal to con-

serve power. If the RC oscillator is used, an external re-

sistor between OSC1 and VSS is required, and the

range of the resistance should be from 30k

W to 680kW.

The system clock, divided by 4, is available on OSC2

Bit No.

Label

Function

INTC

(0BH)

EMI

Controls the Master (Global) interrupt

(1=enabled; 0=disabled)

Unused bit, read as

²0²

ET0I

Controls the Timer Counter 0 interrupt

(1=enabled; 0=disabled)

ET1I

Controls the Timer Counter 1 interrupt

(1=enabled; 0=disabled)

Unused bit, read as

²0²

T0F

Internal Timer Counter 0 request flag

(1=active; 0=inactive)

T1F

Internal Timer Counter 1 request flag

(1=active; 0=inactive)

Unused bit, read as

²0²

INTC register

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