AD7701ARS datasheet(4/21 Pages) AD

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REV. E

AD7701

–3–

Parameter

A, S Version

B, T Version

Unit

Test Conditions/Comments

POWER REQUIREMENTS

Power Supply Voltages

Analog Positive Supply (AVDD)

4.5/5.5

V min/V max

Digital Positive Supply (DVDD)

4.5/AVDD

V min/V max

Analog Negative Supply (AVSS)

–4.5/–5.5

V min/V max

Digital Negative Supply (DVSS)

–4.5/–5.5

V min/V max

Calibration Memory Retention

Power Supply Voltage

2.0

V min

DC Power Supply Currents

Analog Positive Supply (AIDD)

2.7

mA max

Typically 2 mA

Digital Positive Supply (DIDD)2

mA max

Typically 1 mA

Analog Negative Supply (AISS)

2.7

mA max

Typically 2 mA

Digital Negative Supply (DISS)

0.1

mA max

Typically 0.03 mA

Power Supply Rejection

Positive Supplies

dB typ

Negative Supplies

dB typ

Power Dissipation

Normal Operation

mW max

SLEEP = Logic 1,

Typically 25 mW

Standby Operation

20 (40 S Version)

20 (40 T Version)

µW max

SLEEP = Logic 0,

Typically 10

µW

NOTES

1The A

IN pin presents a very high impedance dynamic load that varies with clock frequency.

2Temperature ranges are as follows: A, B Versions: –40

°C to +85°C; S, T Versions: –55°C to +125°C.

3Apply after calibration at the temperature of interest. Full-scale error applies for both unipolar and bipolar input ranges.

4Total drift over the specified temperature range since calibration at power-up at 25

°C. This is guaranteed by design and/or characterization. Recalibration at

any temperature will remove these errors.

5In Unipolar mode, the offset can have a negative value (–V

REF) such that the Unipolar mode can mimic Bipolar mode operation.

6The specifications for input overrange and for input span apply additional constraints on the offset calibration range.

7For Unipolar mode, input span is the difference between full scale and zero scale. For Bipolar mode, input span is the difference between positive and

negative full-scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of

±(V

REF +0.1).

8All digital outputs unloaded. All digital inputs at 5 V CMOS levels.

9Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter.

10CLKIN is stopped. All digital inputs are grounded.

Specifications subject to change without notice.

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