5

TLV705, TLV705P

www.ti.com

SBVS151F – DECEMBER 2010 – REVISED APRIL 2017

Product Folder Links: TLV705 TLV705P

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Copyright © 2010–2017, Texas Instruments Incorporated

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.

(2)

All voltages are with respect to network ground pin.

6 Specifications

6.1 Absolute Maximum Ratings

(1)

MIN

MAX

UNIT

–0.3

6

V

–0.3

6

V

–0.3

6

V

Maximum output current

Internally limited

Output short-circuit duration

Indefinite

Temperature

–55

150

°C

–55

150

°C

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE

UNIT

Electrostatic discharge

±2000

V

±500

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

Input voltage

2

5.5

V

Output voltage

0.7

4.8

V

Output current

0

200

mA

Junction temperature

–40

125

°C

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Thermal Information

TLV705

UNIT

YFF, YFP

(DSBGA)

YFM

(PicoStar)

4 PINS

4 PINS

Junction-to-ambient thermal resistance

160

191.7

°C/W

Junction-to-case (top) thermal resistance

80

3.1

°C/W

Junction-to-board thermal resistance

90

36.5

°C/W

Junction-to-top characterization parameter

0.5

2.8

°C/W

Junction-to-board characterization parameter

78

26.5

°C/W