DP83815 datasheet(7/108 Pages) NSC

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2.0 Pin Description (Continued)

PERRN

I/O

Parity Error: The DP83815 as a master or target will assert this

signal low to indicate a parity error on any incoming data (except for

special cycles). As a bus master, it will monitor this signal on all write

operations (except for special cycles).

REQN

Request: The DP83815 will assert this signal low to request

ownership of the bus from the central arbiter.

RSTN

Reset: When this signal is asserted all outputs of DP83815 will be

tri-stated and the device will be put into a known state.

SERRN

I/O

System Error: This signal is asserted low by DP83815 during

address parity errors and system errors if enabled.

STOPN

I/O

Stop: This signal is asserted low by the target device to request the

master device to stop the current transaction.

TRDYN

I/O

Target Ready: As a master, this signal indicates that the target is

ready for the data during write operation and with the data during

read operation. As a target, this signal will be asserted low when the

(target) device is ready to complete the current data phase

transaction. This signal is used in conjunction with the IRDYN signal.

Data transaction takes place at the rising edge of PCICLK when both

IRDYN and TRDYN are asserted low.

PMEN/

CLKRUNN

I/O

Power Management Event/Clock Run Function: This pin is a dual

function pin. The function of this pin is determined by the

CLKRUN_EN bit 0 of the CLKRUN Control and Status register

(CCSR). Default operation of this pin is PMEN.

Power Management Event: This signal is asserted low by DP83815

to indicate that a power management event has occurred. For pin

connection please refer to Section 6.7.

Clock Run Function: In this mode, this pin is used to indicate when

the PCICLK will be stopped.

3VAUX

122

J11

PCI Auxiliary Voltage Sense: This pin is used to sense the

presence of a 3.3V auxiliary supply in order to define the PME

Support available. For pin connection please refer to Section 6.7.

This pin has an internal weak pull down.

PWRGOOD

123

H13

PCI bus power good: Connected to PCI bus 3.3V power (not

3.3Vaux), this pin is used to sense the presence of PCI bus power.

This pin has an internal weak pull down.

PCI Bus Interface

Symbol

LQFP Pin

No(s)

LBGA Pin

No(s)

Dir

Description

DP83815 Datasheet(PDF) 7 Page - National Semiconductor (TI)

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