AD9670EBZ datasheet(32/53 Pages) AD

32 / 53 page

Data Sheet

AD9670

Rev. A | Page 31 of 52

The format of the output data is twos complement by default.

Table 14 provides an example of the output coding format. To

change the output data format to twos complement, see the

Memory Map section.

Table 14. Digital Output Coding with RF Decimator Bypassed,

Demodulator Bypassed, and Baseband Decimator Bypassed

Code

(VIN+) − (VIN−),

Input Span = 2 V p-p (V)

Digital Output Mode: Twos

Complement (D13 to D0)

16384

+1.00

01 1111 1111 1111

8192

0.00

00 0000 0000 0000

8191

−0.000488

11 1111 1111 1111

−1.00

10 0000 0000 0000

Digital data from each channel is serialized based on the

number of lanes that are enabled (see Table 27). The maximum

data rate for each serial output lane is 1 Gbps. For 1 channel/

lane with a 14-bit data stream and an ADC sample clock of

70 MHz, the output data rate is 980 Mbps (14 bits × 70 MHz =

980 Mbps) with the RF decimator bypassed, the demodulator

bypassed, and the baseband decimator bypassed. For higher

sample rates, enabling the RF decimator is required.

Two output clocks are provided to assist in capturing data from

the AD9670. DCO± clocks the output data and is equal to seven

times the sampling clock rate in 14-bit mode with the RF decimator

bypassed, the demodulator bypassed, and the baseband decimator

bypassed. Data is clocked out of the AD9670 and must be captured

on the rising and falling edges of DCO±, which support double

data rate (DDR) capturing. The frame clock output (FCO±)

signals the start of a new output byte and is equal to the sampling

clock rate.

A 12-, 14-, or 16-bit serial stream can also be initiated from SPI

streams and test device compatibility with lower and higher

resolution systems using these modes.

When using the SPI, all the data outputs can also be inverted

from their nominal state by setting Bit 2 in the output mode

the serial stream to an LSB first mode. In default mode, as shown

in Figure 2, the MSB is represented first in the data output serial

stream. However, this order this can be inverted so that the LSB is

represented first in the data output serial stream.

Output Zero Stuffing

A zero stuffing feature handles the various decimation rates and

complex (IQ) vs. real samples. As the decimation rates increase,

relatively large amounts of zero stuffing can occur in the output

data stream.

AD9670EBZ Datasheet(PDF) 32 Page - Analog Devices

AD9670EBZ Datasheet(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Datasheet Download

Link URL