AD9670EBZ datasheet(52/53 Pages) AD

52 / 53 page

AD9670

Data Sheet

Rev. A | Page 51 of 52

MEMORY MAP REGISTER DESCRIPTIONS

For more information on the SPI memory map and other

functions, consult the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI.

Transfer (Register 0x0FF)

All registers except Register 0x002 are updated the moment they

are written. Setting Bit 0 of Register 0x0FF high initializes and

updates the speed mode (Address 0x002) and resets all other

registers to their default values. Bit 0 is self clearing. It is

recommended that Register 0x002 and Regoster 0x0FF, Bit 0,

be set at the beginning of the setup SPI writes after the device

is powered up. This avoids rewriting other registers after

Profile Index and Manual TX_TRIG (Register 0x10C)

The vector profile is selected using the profile index in

generates a TX_TRIG signal internal to the device. This signal

is asynchronous to the ADC sample clock. Therefore, it cannot

be used to align the data output, advanced power mode, or

NCO reset across multiple devices in the system. The external

pin-driven TX_TRIG control is recommended for systems that

require synchronization of these features across multiple

AD9670 devices.

AD9670EBZ Datasheet(PDF) 52 Page - Analog Devices