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SLG46200 Datasheet(PDF) 39 Page - Dialog Semiconductor |
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SLG46200 Datasheet(HTML) 39 Page - Dialog Semiconductor |
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39 / 69 page ![]() 000-0046200-124 Page 34 of 64 SLG46200 14.0 Power On Reset (POR) The Power On Reset (POR) macro cell will produce a “1” signal as an output when the power supply (VDD) rises to 2.5V or greater. This signal (POR4NVM) requires approximately 3ms of delay before it will go from low to high. When NVM data is ready, the oscillator must be stable at the same time. If the oscillator power on is controlled by auto power on signals such as delay cells, ADC, or PWM, the oscillator will need a maximum of 5 μs to become stable. Figure 19. Power on Reset Timing Diagram Figure 20. Stable Oscillator wait time POR4NVM VDD NVM data ready/ oscillator stable 2.4V ~3ms 22 s Oscillator stable s Oscillator power on control signals |
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