AD7760

Preliminary Technical Data

Rev. PrN | Page 8 of 22

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

AGND

AVDD2

AVDD2

AGND

DB12

DB13

DB14

DB15

VDRIVE

DGND

DGND

DVDD

CS

RD/WR

DRDY

RESET

39

38

37

41

40

SYNC

DGND

AGND

AVDD1

36

35

34

33

42

43

44

45

46

47

48

17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

64 63 62 61 60 59 58

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

AD7760

DGND

MCLK

MCLK

AVDD2

AVDD1

AGND

VREF+

AGND

AVDD4

13

14

15

16

25 26 27

31

30

29

28

32

57 56 55 54 53 52 51 50 49

AGND

DECAP1

REFGND

Figure 5. 64-Lead TQFP Pin Configuration

DB15

PIN 1

IDENTIFIER

AD7760

TOP VIEW

(Not to Scale)

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

9

10

11

12

VDRIVE

MCLK

MCLK

AVDD2

AVDD1

DECAP1

REFGND

VREF+

AVDD4

AVDD2

AVDD2

RBIAS

AVDD1

SYNC

RESET

DRDY

RD/WR

CS

DVDD

VDRIVE

DB14

DB13

DB12

Figure 6. 48-PIN LFCSP Pin Configuration

Table 4. Pin Function Descriptions

TQFP Pin

Number

CSP Pin

Number

Pin Mnemonic

Description

6, 33

5, 25

+2.5V power supply for modulator. These pins should be decoupled to AGND with 100nF and

10µF capacitors on each pin.

4, 14, 15,

27

4, 10, 11,

20

+5V power supply. These pins should be decoupled to AGND with TBD nF and TBD µF

capacitors on each pin.

24

17

+3.3V to +5V power supply for differential amplifier. These pins should be decoupled to AGND

with a 100nF capacitor.

12

9

+3.3V to +5V power supply for reference buffer. This pin should be decoupled to AGND with a

10nF capacitor in series with a 22

Ω resistor.

5, 7, 11,

13, 16, 18,

23, 28, 31,

32, 34

23, 24,

Paddle

AGND

Power supply ground for analog circuitry. In the Chip Scale package, most of the internal

AGND pads are down-bonded to the exposed paddle. This paddle then become the main

analog ground connection for the AD7760.

9

7

REFGND

Reference Ground. Ground connection for the reference voltage.

41

31

+2.5V power supply for digital circuitry and FIR filter. This pin should be decoupled to DGND

with a 470nF capacitor.

44, 63

1, 32

Logic power supply input, +1.8V to +2.5V. The voltage supplied at these pins will determine

the operating voltage of the logic interface. Both these pins must be connected together and

tied to the same supply. Each pin should also be decoupled to DGND with a 470nF capacitor.

1, 35, 42,

43, 53, 62,

64

Paddle

DGND

Ground Reference for digital circuitry. In the Chip Scale package, all the internal DGND pads

are down-bonded to the exposed paddle. This paddle then becomes the single ground

connection for the AD7760.