W134

........................ Document #: 38-07426 Rev. *C Page 3 of 11

Key Specifications

Operating Temperature: ................................... 0°C to +70°C

Input Threshold:...................................................1.5V typical

Maximum Input Frequency: ..................................... 100 MHz

Output Duty Cycle:................................... 40/60% worst case

Output Type: ........................... Rambus signaling level (RSL)

DDLL System Architecture and Gear Ratio

Logic

Figure 1 shows the Distributed Delay Lock Loop (DDLL)

system architecture, including the main system clock source,

the Direct Rambus clock generator (DRCG), and the core logic

that contains the Rambus Access Cell (RAC), the Rambus

Memory Controller (RMC), and the Gear Ratio Logic. (This

diagram abstractly represents the differential clocks as a

single Busclk wire.)

The purpose of the DDLL is to frequency-lock and phase-align

the core logic and Rambus clocks (Pclk and Synclk) at the

RMC/RAC boundary in order to allow data transfers without

incurring additional latency. In the DDLL architecture, a PLL is

used to generate the desired Busclk frequency, while a

distributed loop forms a DLL to align the phase of Pclk and

Synclk at the RMC/RAC boundary.

The main clock source drives the system clock (Pclk) to the

core logic, and also drives the reference clock (Refclk) to the

DRCG. For typical Intel architecture platforms, Refclk will be

half the CPU front side bus frequency. A PLL inside the DRCG

multiplies Refclk to generate the desired frequency for Busclk,

and Busclk is driven through a terminated transmission line

(Rambus Channel). At the mid-point of the channel, the RAC

senses Busclk using its own DLL for clock alignment, followed

by a fixed divide-by-4 that generates Synclk.

Pclk is the clock used in the memory controller (RMC) in the

core logic, and Synclk is the clock used at the core logic

interface of the RAC. The DDLL together with the Gear Ratio

Logic enables users to exchange data directly from the Pclk

domain to the Synclk domain without incurring additional

latency for synchronization. In general, Pclk and Synclk can

be of different frequencies, so the Gear Ratio Logic must

select the appropriate M and N dividers such that the

frequencies of Pclk/M and Synclk/N are equal. In one inter-

esting example, Pclk = 133 MHz, Synclk = 100 MHz, and

M = 4 while N = 3, giving Pclk/M = Synclk/N = 33 MHz. This

example of the clock waveforms with the Gear Ratio Logic is

shown in Figure 2.

The output clocks from the Gear Ratio Logic, Pclk/M, and

Synclk/N, are output from the core logic and routed to the

DRCG Phase Detector inputs. The routing of Pclk/M and

Synclk/N must be matched in the core logic as well as on the

board.

After comparing the phase of Pclk/M vs. Synclk/N, the DRCG

Phase Detector drives a phase aligner that adjusts the phase

of the DRCG output clock, Busclk. Since everything else in the

distributed loop is fixed delay, adjusting Busclk adjusts the

phase of Synclk and thus the phase of Synclk/N. In this

manner the distributed loop adjusts the phase of Synclk/N to

match that of Pclk/M, nulling the phase error at the input of the

DRCG Phase Detector. When the clocks are aligned, data can

be exchanged directly from the Pclk domain to the Synclk

domain.

Table 1 shows the combinations of Pclk and Busclk

frequencies of greatest interest, organized by Gear Ratio.

Pclk

Synclk

Pclk/M =

Synclk/N

Figure 2. Gear Ratio Timing Diagram

Table 1. Supported Pclk and Busclk Frequencies, by Gear Ratio

Pclk

Gear Ratio and Busclk

2.0

1.5

1.33

1.0

67 MHz

267 MHz

100 MHz

300 MHz

400 MHz

133 MHz

267 MHz

356 MHz

400 MHz

150 MHz

400 MHz

200 MHz

400 MHz