CCG3PA datasheet(4/37 Pages) CYPRESS

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Document Number: 002-16951 Rev. *F

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EZ-PD™ CCG3PA Datasheet

Functional Overview

MCU Subsystem

CPU

The Cortex-M0 CPU in EZ-PD CCG3PA is part of the 32-bit MCU

subsystem, which is optimized for low-power operation with

extensive clock gating.

The CPU also includes a serial wire debug (SWD) interface,

which is a 2-wire form of JTAG. The debug configuration used for

EZ-PD CCG3PA has four break-point (address) comparators

and two watchpoint (data) comparators.

Flash

The EZ-PD CCG3PA device has a flash module with one bank

of 64-KB flash, a flash accelerator, tightly coupled to the CPU to

improve average access times from the flash block.

SROM

A supervisory ROM that contains boot and configuration routines

is provided.

USB-PD Subsystem (SS)

The USB-PD subsystem provides the interface to the Type-C

USB port. This subsystem comprises a current sense amplifier,

a high-voltage regulator, OVP, OCP, and supply switch blocks.

This subsystem also includes all ESD required and supported on

the Type-C port.

USB-PD Physical Layer

The USB-PD Physical Layer consists of a transmitter and

receiver that communicate BMC-encoded data over the CC

channel based on the PD 3.0 standard. All communication is

half-duplex. The Physical Layer or PHY practices collision

avoidance to minimize communication errors on the channel.

The USB-PD block includes all termination resistors (RP and RD)

and their switches as required by the USB-PD spec. RP and RD

resistors are required to implement connection detection, plug

orientation detection, and for establishing USB DFP/UFP roles.

The RP resistor is implemented as a current source.

According to the USB Type-C spec, a Type-C controller such as

CCG3PA must present certain termination resistors depending

on its role in its unpowered state. The Sink role in a power bank

application requires RD resistors to be present on the CC pins

whereas the DFP role, as in a power adapter, requires both CC

lines to be open. To be flexible for such applications, CCG3PA

includes the resistors required in the unpowered state on

separate pads or pins. The dead battery RD resistors are

available on separate pads. The dead battery RD is implemented

as a bond option on parts for Power Bank applications. In these

parts, each CC pin is bonded out together with its corresponding

dead battery RD resistor. On part numbers for the DFP appli-

cation, the CC pins are not bonded with the dead battery RD.

ADC

The ADC is a low-footprint 8-bit SAR ADC that is available for

general-purpose A-D conversion applications in the chip. This

ADC can be accessed from all GPIOs and the DP/DM pins

through an on-chip analog mux. CCG3PA contains two instances

of the ADC. The voltage reference for the ADCs is generated

either from the VDDD supply or from internal bandgap. When

sensing the GPIO pin voltage with an ADC, the pin voltage

cannot exceed the VDDIO supply value.

Charger Detection

The two charger detection blocks connected to the two pairs of

DP/DM pins allow CCG3PA to detect conventional battery

chargers conforming to BC 1.2, and the following proprietary

charger specifications: Apple, Qualcomm’s QuickCharge 4.0,

and Samsung AFC.

VBUS Overcurrent and Overvoltage Protection

The CCG3PA chip has an integrated hardware block for VBUS

overvoltage protection (OVP)/overcurrent protection (OCP) with

configurable thresholds and response times on the Type C port.

VBUS Short Protection

CCG3PA provides four VBUS short protection pins: CC1, CC2,

P2.2, and P2.3. These pins are protected from accidental shorts

to high-voltage VBUS. Accidental shorts may occur because the

CC1 and CC2 pins are placed next to the VBUS pins in the USB

Type-C connector. A Power Delivery controller without the

high-voltage VBUS short protection will be damaged in the event

of accidental shorts. When the protection circuit is triggered,

CCG3PA can handle up to 17 V forever and between 17 V to

22 VDC for 1000 hours on the OVT pins. When a VBUS short

event occurs on the CC pins, a temporary high-ringing voltage is

observed due to the RLC elements in the USB Type-C cable.

Without CCG3PA connected, this ringing voltage can be twice

(44 V) the maximum VBUS voltage (21.5 V). However, when

CCG3PA is connected, it is capable of clamping temporary

high-ringing voltage and protecting the CC pin using IEC ESD

protection diodes.

Low-side Current Sense Amplifier (CSA)

The CCG3PA chip also has an integrated low-side current sense

amplifier that is capable of detecting current in the order of

100 mA across a 5 mΩ external resistor. It also supports

constant current mode of operation in power adapter application

as a provider.

PFET Gate Drivers on VBUS Path

CCG3PA has two integrated PFET gate drivers to drive external

PFETs on the VBUS provider and consumer path. The

VBUS_P_CTRL gate driver has an active pull-up, and thus can

drive high, low or High-Z.

The VBUS_C_CTRL gate driver can drive only low or high-Z,

thus requiring an external pull-up. These pins are VBUS

voltage-tolerant.

VBUS Discharge FETs

CCG3PA also has two integrated VBUS discharge FETs used to

discharge VBUS to meet the USB-PD specification timing on a

detach condition. VBUS Discharge FET on the provider side can

be used to accelerate the ramp down of VBUS to default 5V on

the secondary side.

Voltage (VBUS) Regulation

CCG3PA contains an integrated feedback control circuitry (for

AC/DC applications) for secondary side control with analog

regulation of the feedback/cathode pins to achieve the appro-

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