Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

HAR2425 Datasheet(PDF) 27 Page - Micronas

Part # HAR2425
Description  High-Precision Dual-Die Programmable Linear Hall-Effect Sensor Family
PDF  33 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  MICRONAS [Micronas]
Direct Link  http://www.micronas.com
Logo MICRONAS - Micronas

HAR2425 Datasheet(HTML) 27 Page - Micronas

Back Button HAR2425 Datasheet HTML 23Page - Micronas HAR2425 Datasheet HTML 24Page - Micronas HAR2425 Datasheet HTML 25Page - Micronas HAR2425 Datasheet HTML 26Page - Micronas HAR2425 Datasheet HTML 27Page - Micronas HAR2425 Datasheet HTML 28Page - Micronas HAR2425 Datasheet HTML 29Page - Micronas HAR2425 Datasheet HTML 30Page - Micronas HAR2425 Datasheet HTML 31Page - Micronas Next Button
Zoom Inzoom in Zoom Outzoom out
 27 / 33 page
background image
DATA SHEET
HAR 24xy
Micronas
July 14, 2015; DSH000170_001EN
27
4.12.Output Short Detection Parameter
at TJ = 40 °C to +170 °C, Typical Characteristics for TJ = 25 °C, after programming and locking
4.13. Output Voltage in Case of Error Detection
at TJ = 40 °C to +170 °C, Typical Characteristics for TJ = 25 °C, after programming and locking
Fig. 4–5: Behavior of HAR 2425 for different VSUP
Symbol
Parameter
Pin
Min.
Typ.
Max.
Unit
Test Conditions
tOCD
Over Current Detection
Time1)
OUTx
128
µs
tTimeout
Time Period without Over
Current Detection1)
OUTx
256
ms
IOVC
Detectable Output Short
Current1)
OUTx
10
mA
1) Characterized on small sample size, not tested
Symbol
Parameter
Pin
Min.
Typ.
Max.
Unit
Test Conditions
VSUP,DIAG
Supply Voltage required to
get defined Output Voltage
Level1)
VSUPx
2.1
V
VError,Low
Output Voltage Range of
Lower Error Band1)
OUTx
0
4%VSUP
VSUP > VSUP,DIAG
5 k
 >= R
L <= 200 k
VError,High
Output Voltage Range of
Upper Error Band1)
OUTx
96
100
%VSUP
VSUP > VSUP,DIAG
5 k
 >= R
L <= 200 k
1) Characterized on small sample size, not tested
VSUP,DIAG
VSUP,UV
5
VSUP,OV
VSUP [V]
Vout [V]
: Output Voltage will be between VSUP and GND
: CUST_SETUP Register Bit no. 7 set to 1  VOUT 4% VSUP
: CUST_SETUP Register Bit no. 7 set to 0  VOUT 96% VSUP



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com