CCG3 datasheet(6/45 Pages) CYPRESS

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EZ-PD™ CCG3

Document Number: 002-03288 Rev. *J

Page 6 of 45

The Overvoltage/Undervoltage (OV/UV) block monitors the

VBUS_C

supply

for

programmable

overvoltage

and

undervoltage conditions. The CSA amplifies the voltage across

an external sense resistor, which is proportional to the current

being drawn from the external DC-DC VBUS supply converter.

The CSA output can either be measured with an ADC or

configured to detect an overcurrent condition. The VBUS_P and

VBUS_C gate drivers control the gates of external power FETs

for the VBUS_C and VBUS_P supplies. The gate drivers can be

configured to support both P and N type external power FETs.

The gate drivers are configured by default for nFET devices. In

applications using pFETs, the gate drivers must be appropriately

configured. The OV/UV and CSA blocks can generate interrupts

to automatically turn off the power FETs for the programmed

overvoltage and overcurrent conditions. The VBUS_C discharge

switch allows for discharging the VBUS_C line through an

external resistor.

The USB-PD subsystem also contains two 8-bit Successive

Approximation Register (SAR) ADCs for analog to digital

conversions. The voltage reference for the ADCs is generated

from the VDDD supply. Each ADC includes an 8-bit DAC and a

comparator. The DAC output forms the positive input of the

comparator. The negative input of the comparator is from a

4-input multiplexer. The four inputs of the multiplexer are a pair

of global analog multiplex busses, an internal bandgap voltage

and an internal voltage proportional to the absolute temperature.

Each GPIO pin can be connected to the global Analog Multiplex

Busses through a switch, which allows either ADC to sample the

pin voltage. When sensing the GPIO pin voltage with an ADC,

the pin voltage cannot exceed the VDDIO supply value.

Figure 2. USB-PD Subsystem

Full-Speed USB Subsystem

The FSUSB subsystem contains a full-speed USB device

controller as described in the Integrated Billboard Device

section.

Peripherals

Serial Communication Blocks (SCB)

EZ-PD CCG3 has four SCBs, which can be configured to

implement an I2C, SPI, or UART interface. The hardware I2C

blocks implement full multi-master and slave interfaces capable

of multimaster arbitration. In the SPI mode, the SCB blocks can

be configured to act as master or slave.

In the I2C mode, the SCB blocks are capable of operating at

speeds of up to 1 Mbps (Fast Mode Plus) and have flexible

buffering options to reduce interrupt overhead and latency for the

CPU. These blocks also support I2C that creates a mailbox

address range in the memory of EZ-PD CCG3 and effectively

reduce I2C communication to reading from and writing to an

array in memory. In addition, the blocks support 8-deep FIFOs

for receive and transmit which, by increasing the time given for

the CPU to read data, greatly reduce the need for clock

stretching caused by the CPU not having read data on time.

The I2C peripherals are compatible with the I2C Standard-mode,

Fast-mode, and Fast-mode Plus devices as defined in the NXP

I2C-bus specification and user manual (UM10204).

The I2C bus I/Os are implemented with GPIO in open-drain

modes.

VBUS_C

V5V

LDO

POWER

SWITCH

charger

dc-dc

OV/UV

CSA

VSYS

VDDD

VCONN

Leaker

PRODUCER N/PFETs

VBUS_P_CTRL

Gate

Driver

Gate

Driver

VBUS_C_CTRL

VBUS_DISCHARGE

CHARGER

DETECT

ANALOG

CROSS-BAR

PROGRAMMABLE

PULL-UP, PULL-DOWN

AUX_P

AUX_N

USB 2.0

FS PHY

BMC

PHY w/ FRS

VBUS_P

VCONN

SWITCH

CONSUMER N/PFETs

CC1

CC2

SBU1

SBU2

USB PD SubSystem

ADCs

HPD

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