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CCG3 Datasheet(PDF) 9 Page - Cypress Semiconductor

Part # CCG3
Description  USB Type-C Port Controller
PDF  45 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CCG3 Datasheet(HTML) 9 Page - Cypress Semiconductor

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EZ-PD™ CCG3
Document Number: 002-03288 Rev. *J
Page 9 of 45
Pinouts
Table 2. CCG3 Pin Description for 42-CSP, 32-QFN, and 40-QFN Devices
Pin Map
42-CSP
Pin Map
32-QFN
Pin Map
40-QFN
Name
Description
A5
1
1
VBUS_P_CTRL1
VBUS Gate Driver Control 1 for Producer Switch
A6
1
2
VBUS_P_CTRL0
VBUS Gate Driver Control 0 for Producer Switch
B6
2
3
CC2
USB PD connector detect/Configuration Channel 2
C5
N/A
N/A
CC2
USB PD connector detect/Configuration Channel 2
D4
3
4
V5V
Input Supply Voltage for VCONN FETs
V5V = 5.0V – 5.5V to supply VCONN > 4.75V @ 1.5W
V5V = 3.5V – 5.5V to supply VCONN > 3.00V @ 1W
C6
4
5
CC1
USB PD connector detect/Configuration Channel 1
D6
N/A
N/A
CC1
USB PD connector detect/Configuration Channel 1
E6
N/A
6
VCONN
VCONN Input - provides RA termination for cable
applications
F6
5
7
P1.0
GPIO/UART_2_TX / SPI_2_MISO
D5
N/A
8
P1.1
GPIO/UART_2_RX / SPI_2_SEL
E5
6
9
P1.2
GPIO/UART_0_RX/ UART_3_CTS/ SPI_3_MOSI/
I2C_3_SCL
G6
7
10
P1.3
GPIO/UART_0_TX/ UART_3_RTS/ SPI_3_CLK/
I2C_3_SDA
E4
N/A
11
AUX_P / P1.6
DisplayPort AUX_P signal / GPIO / UART_1_TX /
SPI_1_MISO
F5
8
12
SBU1 / P1.4
USB Type-C SBU1 signal / GPIO / UART_3_TX/
SPI_3_MISO/ SWD_1_CLK
G5
9
13
SBU2 / P1.5
USB Type-C SBU2 signal / GPIO / UART_3_RX/
SPI_3_SEL/ SWD_1_DAT
G4
N/A
14
AUX_N / P1.7
DisplayPort AUX_N signal / GPIO / UART_1_RX /
SPI_1_SEL
F4
10
15
P2.0
GPIO / UART_1_CTS / SPI_1_CLK/ I2C_1_SCL /
SWD_0_DAT
G3
11
16
P2.1
GPIO / UART_1_RTS / SPI_1_MOSI/ I2C_1_SDA /
SWD_0_CLK
G2
13
17
VDDD
VDDD supply Input / Output (2.7 V–5.5 V)
F3
14
18
VDDIO
1.71 V–5.5 V supply for I/Os. This supply also powers the
global analog multiplex buses.
F2
15
19
VCCD
1.8-V regulator output for filter capacitor
G1
16
20
VSYS
System power supply (2.7 V–5.5 V)
F1
17
21
DPLUS
USB 2.0 DP
E1
18
22
DMINUS
USB 2.0 DM
E2
19
23
P2.4
GPIO
D3
20
24
P2.5
GPIO / UART_0_TX/ SPI_0_MOSI
D2
N/A
25
P2.6
GPIO / UART_0_RX/ SPI_0_CLK
D1
21
26
XRES
External Reset Input. Internally pulled-up to VDDIO.
C3
22
27
P0.0
I2C_0_SDA / GPIO_OVT / UART_0_CTS / SPI_0_SEL/
TCPWM0



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