CY7C1069G

CY7C1069GE

16-Mbit (2M words × 8 bit) Static RAM

with Error-Correcting Code (ECC)

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

•

408-943-2600

Document Number: 001-81539 Rev. *J

Revised December 5, 2017

16-Mbit (2M words × 8 bit) Static RAM with Error-Correcting Code (ECC)

Features

correction

to 5.5 V

packages

Functional Description

The CY7C1069G and CY7C1069GE are dual chip enable

high-performance CMOS fast static RAM devices with

embedded ECC. The CY7C1069G device is available in

standard pin configurations. The CY7C1069GE device includes

a single bit error indication pin (ERR) that signals the host

processor in the case of an ECC error-detection and correction

event.

HIGH) and Write Enable (WE) input LOW. Data on the eight I/O

HIGH) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. Under these conditions, the contents of the

memory location specified by the address pins will appear on the

I/O pins. See Truth Table – CY7C1069G/CY7C1069GE on page

14 for a complete description of Read and Write modes. The

On CY7C1069GE devices, the detection and correction of a

single-bit error in the accessed location is indicated by the

CY7C1069G and CY7C1069GE devices are available in a

54-pin TSOP II package with center power and ground

(revolutionary) pinout, and in a 48-ball VFBGA package.

For a complete list of related documentation, here.

Note

1. Automatic write back on error detection feature is not supported in this device.