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LTC4212CMS Datasheet(PDF) 9 Page - Linear Technology |
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LTC4212CMS Datasheet(HTML) 9 Page - Linear Technology |
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9 / 24 page ![]() 9 LTC4212 4212f PI FU CTIO S – + SLOW COMP 50mV 150mV 0.2V COMP7 M3 18 µS GLITCH FILTER UVLO – + FAST COMP 500ns DELAY BG VREF = 1.236V 0.2V CB TRIPS OR UVLO ON LOW >10 µs START-UP CURRENT REGULATOR GATE CHARGING 200 µA10µA CB TRIPS VREF 10 µA 7 GATE 8 SENSE 9 VCC CHARGE PUMP Z1 VZ (TYP) = 12V M2 GND 5 FAULT 10 – + 4212 BD – + – + COMP3 tTIMER 0.2V VREF COMP4 NORMAL TIMER 2 ON 1 2 µA M6 VCC M5 COMP6 Z2 VZ (TYP) = 28V VCC 1.316V 0.455V 1.5 µs DELAY VREF 4 PGF COMP5 M12 M9 M8 3 PGT COMP9 M1 M10 5 µA 5 µA 5 µA VREF 0.65V 0.95V DISABLE GLITCH FILTER VALID GLITCH DISABLE TIMER 6 PGI COMP8 + – + – COMP2 COMP1 LOGIC 10 µs 120 µs 200 µA GATE PULLDOWN RESET ECB 0.95V 0.65V BLOCK DIAGRA FAULT (Pin 10): Open Drain FAULT Output or External FAULT Input. If the FAST COMP, SLOW COMP or the power good circuit trips the ECB, the FAULT pin is latched low. The FAULT pin is an open drain output and is typically connected by a 10k pull-up resistor to VCC. An external circuit can also trip the ECB by driving FAULT below 1.236V (typical). |
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