PIC16F818-ESLASHML datasheet(23/176 Pages) MICROCHIP

23 / 176 page

 2004 Microchip Technology Inc.

DS39598E-page 21

PIC16F818/819

2.2.2.6

PIE2 Register

The PIE2 register contains the individual enable bit for

the EEPROM write operation interrupt.

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS 8Dh)

2.2.2.7

PIR2 Register

The PIR2 register contains the flag bit for the EEPROM

write operation interrupt.

PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ADDRESS 0Dh)

U-0

R/W-0

U-0

—

EEIE

—

bit 7

bit 0

bit 7-5

Unimplemented: Read as ‘0’

bit 4

EEIE: EEPROM Write Operation Interrupt Enable bit

= Enable EE write interrupt

= Disable EE write interrupt

bit 3-0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

Note:

Interrupt flag bits are set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE (INTCON<7>).

User software should ensure the appropri-

ate interrupt flag bits are clear prior to

enabling an interrupt.

U-0

R/W-0

U-0

—

EEIF

—

bit 7

bit 0

bit 7-5

Unimplemented: Read as ‘0’

bit 4

EEIF: EEPROM Write Operation Interrupt Enable bit

= Enable EE write interrupt

= Disable EE write interrupt

bit 3-0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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