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PIC16F818-E/ML Datasheet(PDF) 80 Page - Microchip Technology

Part # PIC16F818-E/ML
Description  18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Technology
PDF  176 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16F818-E/ML Datasheet(HTML) 80 Page - Microchip Technology

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PIC16F818/819
DS39598E-page 78
 2004 Microchip Technology Inc.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
the data transfer is complete. When the ACK is latched
by the slave device, the slave logic is reset (resets
SSPSTAT register) and the slave device then monitors
for another occurrence of the Start bit. If the SDA line
was low (ACK), the transmit data must be loaded into
the SSPBUF register which also loads the SSPSR
register. Then pin RB4/SCK/SCL should be enabled by
setting bit, CKP.
TABLE 10-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
FIGURE 10-6:
I2C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
FIGURE 10-7:
I2C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Status Bits as Data
Transfer is Received
SSPSR
→ SSPBUF
Generate ACK Pulse
Set bit SSPIF
(SSP interrupt occurs if enabled)
BF
SSPOV
00
Yes
Yes
Yes
10
No
No
Yes
11
No
No
Yes
0
1
No
No
Yes
Note 1:
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
P
9
8
7
6
5
D0
D1
D2
D3
D4
D5
D6
D7
S
A7 A6 A5 A4 A3 A2 A1
SDA
SCL
12
3
4
5
6
7
8
9
12
3
4
56
7
89
12
3
4
Bus master
terminates
transfer
Bit SSPOV is set because the SSPBUF register is still full
Cleared in software
SSPBUF register is read
ACK
Receiving Data
Receiving Data
D0
D1
D2
D3
D4
D5
D6
D7
ACK
R/W = 0
Receiving Address
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
ACK
ACK is not sent
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
A7
A6
A5
A4
A3
A2
A1
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Transmitting Data
R/W = 1
Receiving Address
1
2
3
4
5678
9
123
4
5
67
8
9
P
Cleared in software
SSPBUF is written in software
Set bit after writing to SSPBUF
S
Data is
Sampled
(the SSPBUF must be written to
before the CKP bit can be set)
From SSP Interrupt
Service Routine
SCL held low
while CPU
responds to SSPIF



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