MP5032

– QC 3.0 CONTROLLER WITH CURRENT-LIMIT SWITCH

MP5032 Rev r1.0

www.MonolithicPower.com

15

8/4/2017

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© 2017 MPS. All Rights Reserved.

APPLICATION INFORMATION

Selecting the Input Capacitor

Use

low

ESR

capacitors

for

the

best

performance. Ceramic capacitors with X5R or

X7R

dielectrics

are

highly

recommended

because

of

their

low

ESR

and

small

temperature

coeff

icients. A 22μF ceramic

capacitor is recommended for most applications.

The input capacitor must also consider pre-

stage converter stability. The input capacitor of

the MP5032 is the output capacitor of the

converter. Ensure that the converter is stable

with an additional output capacitor.

Selecting the Output Capacitor

Use

low

ESR

capacitors

for

the

best

performance. Ceramic capacitors with X5R or

X7R

dielectrics

are

highly

recommended

because

of

their

low

ESR

and

small

temperatur

e coefficients. A 22μF ceramic

capacitor is recommended for most applications.

Selecting the ILIM Resistor

The current limit value can be set by the ILIM

resistor. The programmable current limit can be

calculated with Equation (2). The minimum

current limit should be set higher than the

system

’s full load current.

ADJ has a controlled current sink internally.

Through ADJ, the line drop compensation and

QC mode transition is achieved. The ADJ sink

current capability is 500µA. It is recommended

that the pre-side converter use a k

Ω level

feedback resistor. The current through the high-

side feedback resistor must be less than 500µA.

maximum output voltage (i.e.: to insert R5

between FB and ADJ). With R5, the maximum

output voltage is limited by Equation (3):

 

 

V

V

//R

R

//R

R

R

V

V

FB

5

2

5

2

1

OUT _MAX







(3)

The required feedback resistor of R1 must be

greater than 30k

Ω (see Figure 8).

IN

ADJ

MP5032

C1

Converter

OUT

FB

R1

R2

R5

Other Considerations

The upstream DC/DC converter must have a

current-limit threshold higher than the MP5032's

current limit.

PCB Layout Guidelines

Efficient

PCB

layout

is

critical for

stable

operation and thermal dissipation. For best

results, refer to Figure 9 and follow the

guidelines below.

1. Use short, direct, and wide traces to

connect the IC’s in/out.

2. Keep the ADJ trace to the upstream

converter

’s FB pin as short as possible.

3. Route the ADJ trace as far from the

switching node as possible to avoid noise

injection.

DP

DM

ADJ

EN

OUT

IN

GND

ILIM

FB

DC/DC

VBUS

GND

DP

DM

GND

OUT

IN

C1

GND

R5

Top Layer

Bottom Layer

Figure 9: Recommended Layout