MP8765 ─ 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

MP8765 Rev. 1.01

www.MonolithicPower.com

16

2/10/2015

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APPLICATION INFORMATION

Setting the Output Voltage---without external

compensation

For applications that electrolytic capacitor or POS

capacitor with a controlled output of ESR is set

as

output

capacitors,

or

the

internal

compensation is enough for a stable operation

when ceramic capacitors is used, then the

external compensation is not need.. The output

voltage is set by feedback resistors R1 and R2.

As Figure 10 shows.

R1

R2

ESR

POSCAP

SW

FB

Vo

L

Figure10—Simplified Circuit of POS Capacitor

First, choose a value for R2. R2 should be

chosen reasonably, a small R2 will lead to

considerable quiescent current loss while too

large R2 makes the FB noise sensitive. It is

recommended to choose a value within 5kΩ-

100kΩ for R2.Typically, set the current through

R2 between 5-30uA will make a good balance

between system stability and also the no load

loss. Then R1 is determined as follow with the

output ripple considered:

OUT

OUT

REF

12

REF

1

VV

V

2

RR

V

−Δ

−

=⋅

(13)

OUT

V

Δ

is the output ripple.

Setting the Output Voltage---with external

compensation

R1

R2

Ceramic

SW

FB

Vo

L

R9

R4

C4

Figure11—Simplified Circuit of Ceramic

Capacitor

If the system is not stable enough when low ESR

ceramic capacitor is used in the output, an

external voltage ramp should be added to FB

through resistor R4 and capacitor C4.The output

besides R divider as shown in Figure 11. The

R2 should be chosen reasonably, a small R2 will

lead to considerable quiescent current loss while

too large R2 makes the FB noise sensitive. It is

recommended to choose a value within 5kΩ-

100kΩ for R2.Typically, set the current through

R2 between 5-30uA will make a good balance

between system stability and also the no load

loss. And the value of R1 then is determined as

follow:

2

1

FB(AVG)

2

OUT

FB(AVG)

4

9

R

R=

V

R

-

(V

-V

) R +R

(14)

condition, etc., its value on the skip mode would

be lower than that of the PWM mode, which

means the load regulation is strictly related to the

regulation, a lower Vramp is suggested, as long

as the criterion shown in equation 8 can be met.

deduced from the equation below.

12

FB(AVG)

REF

RAMP

12

9

R//R

1

VV

V

2R //R

R

=+

×

+

(15)

Usually, R9 is set to 0Ω, and it can also be set

following equation 14 for a better noise immunity.

It should also set to be 5 times smaller than

R1//R2 to minimize its influence on Vramp.

9

4SW

1

R

2C

2F

=

π×

×

(16)

Using equation 13 to calculate the R1 can be

complicated. To simplify the calculation, a DC-

blocking capacitor Cdc can be added to filter the

DC influence from R4 and R9. Figure 12 shows

a

simplified

circuit

with

external

ramp

compensation and a DC-blocking capacitor. With

this capacitor, R1 can easily be obtained by