LTC4371 datasheet(3/22 Pages) LINER

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LTC4371

4371f

For more information www.linear.com/LTC4371

elecTrical characTerisTics The

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C, IZ = 50µA, VDD = 12.4V, SA = SB = VSS unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VDD

Input Supply Range

4.5

IDD

Input Supply Current

Normal Operation

Gate Fault to VSS ,Strong Pull-Up Disabled

Gate Fault to VSS, Strong Pull-Up Enabled

∆VSD = ±0.1V

VZ = 10.4V, ∆VSD = 0.1V, One GATE = VSS

IZ = 50µA, ∆VSD = 0.1V, One GATE = VSS

200

400

4.5

300

550

450

750

9.5

µA

Shunt Regulator Voltage

IZ = 50µA

11.8

12.4

∆VZ

Shunt Regulator Load Regulation

IZ = 50µA to 10mA

600

VZ(PU)

VZ High Threshold to Enable Strong Gate Pull-Up VDD = VZ Rising

10.7

11.2

11.8

∆VZ(PU)

VZ High Threshold Hysteresis

0.5

VZ(PU)

VZ Low Threshold to Enable Strong Gate Pull-Up VZ Falling

1.15

1.25

1.35

∆VSD

Source-Drain Forward Servo Voltage

∆VGATE

Gate Drive (VG – VS)

IG = 0µA, –1µA; ∆VSD = 100mV

VDD – 0.2

VDD + 0.1

IGATE(UP) Gate Pull-Up Current

∆VSD = 100mV, ∆VGATE = 5V

–3

–5

–8

IGATE(DN) Gate Pull-Down Current

Strong Gate Pull-Down Current

∆VSD = –10mV, ∆VGATE = 5V

∆VSD = –100mV, ∆VGATE = 5V

tOFF

Gate Turn-Off Time in Fault Condition

∆VSD = 0.1V Step to –0.4V,

CGATE = 3.3nF, ∆VGATE <1V

220

DA, DB Leakage Current

MOSFET Off

MOSFET Open

VD = 80V

VD = –40V

–10

µA

DA, DB Resistance

∆VSD = –50mV to 0.1V

MΩ

VBVD

DA, DB Breakdown Voltage

ID = 10mA, 6ms

100

130

170

SA, SB Leakage Current

VS = 0V

±2

μA

∆VSD(FLT) Source-Drain Fault Detection Threshold

150

200

225

VFAULTB

FAULTB Output Low

IFAULTB = 5mA

0.4

IFAULTB

FAULTB Leakage Current

VFAULTB = 16V

±1

μA

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into pins are positive; all voltages are referenced to

VSS unless otherwise specified.

Note 3: An internal clamp limits the DA and DB pins to a minimum of

100V above VSS and –40V below VSS. This pin can be safely tied to higher

voltages through a resistance that limits the current below 1mA DC or

10mA for a 6ms transient. Driving this pin with current beyond the clamp

may damage the device.

Note 4: Thermal resistance is specified with exposed pad soldered to a

3-inch by 4.5-inch, four layer FR4 board. If exposed pad is not soldered

θJA = 93°C/W.

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