13 / 19 page
CY2277A
Document #: 38-07332 Rev. *A
Page 13 of 19
Timing Requirement for the SMBus
Parameter
Description
Min.
Max.
Unit
t10
SCLK Clock Frequency
0
100
kHz
t11
Time the bus must be free before a new transmission can start
4.7
µs
t12
Hold time start condition. After this period the first clock pulse is generated.
4
µs
t13
The LOW period of the clock.
4.7
µs
t14
The HIGH period of the clock.
4
µs
t15
Setup time for start condition. (Only relevant for a repeated start condition.)
4.7
µs
t16
Hold time DATA
for CBUS compatible masters.
for SMBus devices
5
0
µs
t17
DATA input set-up time
250
ns
t18
Rise time of both SDATA and SCLK inputs
1
µs
t19
Fall time of both SDATA and SCLK inputs
300
ns
t20
Set-up time for stop condition
4.0
µs
Switching Waveforms
Duty Cycle Timing
t1A
t1B
CPUCLK Outputs HIGH/LOW Time
OUTPUT
VDD
0V
t1C
t1D
All Outputs Rise/Fall Time
OUTPUT
t2
t3
VDD
0V
t2
t4
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
