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LTM4623 Datasheet(PDF) 20 Page - Linear Technology |
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LTM4623 Datasheet(HTML) 20 Page - Linear Technology |
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20 / 28 page ![]() LTM4623 20 4623fc For more information www.linear.com/LTM4623 applicaTions inForMaTion Table 7. Output Voltage Response vs Component Matrix (Refer to Figure 24) CIN PART NUMBER VALUE COUT1 PART NUMBER VALUE Murata GRM21BR61E106KA73L 10µF, 25V, 0805, X5R Murata GRM21BR60J476ME15 47µF, 6.3V, 0805, X5R Taiyo Yuden TMK212BBJ106KG-T 10µF, 25V, 0805, X5R Taiyo Yuden JMK212BJ476MG-T 47µF, 6.3V, 0805, X5R Murata GRM31CR61C226ME15L 22µF, 25V, 1206, X5R Taiyo Yuden TMK316BBJ226ML-T 22µF, 25V, 1206, X5R VOUT (V) CIN (CERAMIC) (µF) COUT1 (CERAMIC) (µF) CFF (pF) VIN (V) DROOP (mV) P-P DERIVATION (mV) RECOVERY TIME (µs) LOAD STEP (A) LOAD STEP SLEW RATE (A/µs) RFB (kΩ) FREQ (MHz) 1 10 47 100 5, 12 1 59 40 1 1 90.9 1 1.2 10 47 100 5, 12 1 59 40 1 1 60.4 1 1.5 10 47 100 5, 12 1 66 40 1 1 40.2 1 1.8 10 47 100 5, 12 1 75 40 1 1 30.1 1 2.5 10 47 100 5, 12 2 108 50 1 1 19.1 1 3.3 10 47 100 5, 12 3 111 60 1 1 13.3 2 5 10 47 100 12 5 156 60 1 1 8.25k 2 Safety Considerations The LTM4623 modules do not provide galvanic isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. The device does support thermal shutdown and overcurrent protection. Layout Checklist/Example The high integration of LTM4623 makes the PCB board layoutverysimpleandeasy.However,tooptimizeitselectri- cal and thermal performance, some layout considerations are still necessary. • Use large PCB copper areas for high current paths, including VIN, GND and VOUT. It helps to minimize the PCB conduction loss and thermal stress. • Place high frequency ceramic input and output capaci- tors next to the VIN, PGND and VOUT pins to minimize high frequency noise. • Placeadedicatedpowergroundlayerunderneaththeunit. • To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. • Do not put via directly on the pad, unless they are capped or plated over. Table 5. 3.3V Output, No Heat Sink DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK θJA(°C/W) Figures 18, 19, 20 5, 12, 16 Figure 10 0 None 25 Figures 18, 19, 20 5, 12, 16 Figure 10 200 None 22 Figures 18, 19, 20 5, 12, 16 Figure 10 400 None 22 Table 6. 5V Output, No Heat Sink DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK θJA(°C/W) Figures 21, 22 12, 16 Figure 11 0 None 25 Figures 21, 22 12, 16 Figure 11 200 None 22 Figures 21, 22 12, 16 Figure 11 400 None 22 |
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