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LT8603

8603f

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APPLICATIONS INFORMATION

by several factors including the accuracy and temperature

coefficient of the capacitor CPOR, parasitic capacitance

on the CPOR pin and board trace, and system noise. It

is not recommended to use capacitor values greater than

10nF for best accuracy. Figure 11 shows the power-on

reset timing.

General: Sequencing

The LT8603 provides flexibility in sequencing each chan-

nel’s output including a power-on reset timer. Each chan-

nel has a power good output (PG1 to PG4) and input

control pin or pins (TRKSS1, TRKSS2, RUN3, FSEL4A,

and FSEL4B). The POR has a control input (POREN) and

For each buck regulator, the current loop formed by the

input capacitor has the highest di/dt and should be made

as small as possible by placing the input capacitor close

to the PVIN pin and the adjacent GND pin. When using a

physically large input capacitor, the resulting loop may

be larger than optimum. In this case using a small case/

value capacitor placed close to the PVIN and GND pins

plus a larger capacitor further away is preferred. These

components, along with the inductor and output capacitor,

should be placed on the same side of the circuit board,

and their connections made on that layer.

The boost controller output loop, including the diode and

output capacitor components, has the highest di/dt. As a

result, the loop involving the diode and output capacitor

should be kept as small as possible.

Place a local, unbroken ground plane under the applica-

tion circuit on the layer closest to the surface layer. The

SW and BST nodes should be made as small as possible

to minimize noise coupling to sensitive traces. Minimize

traces connecting to the RT and all FB pins and provide

ground shielding as needed to minimize noise coupling

to these sensitive nodes.

The exposed pad on the bottom of the package must have

a good electrical and thermal connection to the board

ground. For best performance, maximize board ground

planes and thermal vias under and near the part.

Figure 11. Power-On Reset Timing

1ms/DIV

POREN

1V/DIV

CPOR

1V/DIV

RST

2V/DIV

8601 F11

a reset output (RST). All 5 outputs are open-drain. A

sequencing example is shown in Figure 12.

In this example, Channel 4 starts first and soft-starts inter-

nally. When Channel 4 reaches regulation, Channels 1 and

2 start up and ramp according to R1/CTRKSSx. Once both

VOUT1 and VOUT2 reach regulation, Channel 3 starts. When

OUT3 is in regulation, then the POR timer is started.

PCB LAYOUT

For proper operation and minimum EMI, care must

be taken during printed circuit board layout. A recom-

mended board layout is available with the latest LT8603

demo board. Some general guidelines are available in the

remainder of this section.

Figure 12. Sequencing the Outputs and POR

8603 F12

POREN

RST

CPOR

FSEL4B

PG3

PG2

LT8603

PG1

RUN3

TRKSS2

TRKSS1

PG4

FSEL4A

INTVCC

R2 R3

RESET

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