Functional Description

SERIAL BUS OPERATION

Bus Overview

The MPL bus is a simple 2-signal line interface that is

intended to replace wide low voltage CMOS video busses

inside handheld portable devices. The MPL physical layer is

purpose-built for an extremely low power and low EMI data

transmission while requiring the fewest number of signal

lines. No external line components are required, as termina-

tion is provided internal to the MPL receiver. The MPL inter-

face is designed to be used with common 50

Ω lines using

standard materials and connectors. Lines may be microstrip

or stripline construction. Total length of the interconnect is

expected to be less than 0.3 meters. This device is meets

the requirements of the MPL-0 Standard (PHY Layer only).

SERIAL BUS TIMING

Data valid is relative to both edges as shown in Figure 4.

Data valid is specified as: Data Valid before Clock, Data

Valid after Clock, (Note relative to both edges).

SERIAL BUS PHASES

There are three bus phases on the MPL serial bus. These

are determined by the state of the MC and MD lines. Two of

the bus phases have options. The MPL bus phases are

shown in Table 1.

TABLE 1. MPL Bus Phases

Name

WC State

MC State

MD State

Phase Description

Pre-Phase

Post-Phase

OFF (O)

0

0

0

Bus is Powered-Off

na

I (WC)

Initialization (I)

WC

A

0

0

WC Start Up

O

I (MC)

MC/MD

A

A

0

MPL Start Up

I (WC)

A

Active (A)

A

A

X

Data Out (Write)

I (MC)

A or O

Notes on Line State: 0 = no current (off), L = Logic Low, H = Logic High, X = Low or High, A — Active Clock

20091602

FIGURE 4. Master-to-Slave Timing (MC, MDm)

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