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HMC8410LP2FE Datasheet(PDF) 14 Page - Analog Devices

Part # HMC8410LP2FE
Description  Low Noise Amplifier
PDF  17 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

HMC8410LP2FE Datasheet(HTML) 14 Page - Analog Devices

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HMC8410
Data Sheet
Rev. A | Page 14 of 17
APPLICATIONS INFORMATION
Figure 38 shows the basic connections for operating the
HMC8410. AC couple the input and output of the HMC8410
with appropriately sized capacitors. DC block capacitors and RF
choke inductors are supplied on the RFIN and RFOUT pins of
the HMC8410 evaluation board. See Table 6 for additional
information. These dc block capacitors and RF choke inductors
form wideband bias tees on the input and output ports to provide
both ac coupling and the necessary supply voltages to the RFIN
and RFOUT pins. A 5 V dc bias is supplied to the amplifier
through the choke inductor connected to the RFOUT pin, and
the negative VGG1 voltage is supplied to the RFIN pin through
the choke inductor.
RECOMMENDED BIAS SEQUENCING
To not damage the amplifier, follow the recommended bias
sequencing.
During Power-Up
The recommended bias sequence during power-up for the
HMC8410 follows:
1. Connect to GND.
2. Set VGG1 to −2 V.
3. Set VDD to +5 V.
4. Increase VGG1 to achieve a typical supply current (IDQ) =
65 mA.
5. Apply the RF signal.
During Power-Down
The recommended bias sequence during power-down for the
HMC8410 follows:
1. Turn off the RF signal.
2. Decrease VGG1 to −2 V to achieve a typical IDQ = 0 mA.
3. Decrease VDD to 0 V.
4. Increase VGG1 to 0 V.
The bias conditions previously listed (VDD = 5 V and IDQ =
65 mA) are the recommended operating points to achieve
optimum performance. The data used in this data sheet was
taken with the recommended bias conditions. When using the
HMC8410 with different bias conditions, different performance
than what is shown in the Typical Performance Characteristics
section may result.
Figure 18, Figure 30, and Figure 31 show that increasing the
voltage from 2 V to 7 V typically increases P1dB and PSAT at the
expense of power consumption with minor degradation on
noise figure (NF).
TYPICAL APPLICATION CIRCUIT
PACKAGE
BASE
GND
VDD
RFOUT
J2
RFIN/VGG1
J1
L2
590nH
C4
20pF
C5
2.2µF
C5
10nF
+
6
5
1
2
3
4
HMC8410
VGG1
L2
590nH
C15
20pF
C14
4.7µF
C13
100nF
+
Figure 38. Typical Application Circuit



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