MP6520

– 32V, 1.5A, MICROSTEPPING MOTOR DRIVER W/ INTEGRATED MOSFETS

MP6520 Rev. 1.0

www.MonolithicPower.com

10

10/10/2016

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Microstep Selection (MS1, MS2)

The step mode is selected by applying logic-

high and -low voltages to the MS1 and MS2

input pins. The MP6520 supports full-, half-,

quarter-, and eighth-step modes.

Full-step has four states with each motor

winding driven with either 70.7% maximum

positive current or 70.7% maximum negative

current. This provides four steps per electrical

rotation. Half-step provides eight steps per

electrical rotation; quarter-step provides 16

steps

per

electrical

rotation;

eighth-step

provides 32 steps per electrical rotation. Refer

to Table 3 and Figure 3 for details.

Table 2 shows step modes selected for different

settings of the MS1 and MS2 input pins.

Table 2: Stepping Format

MS2

MS1

Step Mode

L

L

Full-step

L

H

Half-step

H

L

Quarter-step

H

H

Eighth-step

Decay Modes

During PWM off-time, the output current decay

can operate in slow, fast, or mixed decay

depending on the voltage level at the MDS

input and any current change commanded by a

STEP transition.

If the voltage on the MDS input pin is less than

2.5V,

then

mixed

decay

mode

with

an

adjustable fast decay ratio is selected. The time

that the device operates in fast decay can be

approximated with Equation (4):

FD

mds

OFF

t

V

(V) 0.4 t







(4)

switches to slow decay mode for the remainder

of the constant-off-time period. Note that if MDS

is set to 0V (connected to ground), slow decay

is used for the entire off time.

If the voltage at the MDS input is greater than

2.8V, then automatic decay mode is selected.

In automatic decay mode, if the commanded

current level is equal to or higher than the level

at the previous step, then slow decay is

selected. If the current level is lower than

previous level, then mixed decay with a fixed

30% fast decay ratio is selected.

nRSET, nSLEEP, and nENBL Operation

When nRSET is driven logic low, the step table

is reset to the home position (see Table 3). The

STEP input signal is ignored while nRSET is

low.

Driving nSLEEP low puts the device into a low

power sleep state. In this state, all internal

circuits including the gate drive charge pump

and the 3P3VOUT regulator are disabled. The

H-bridge outputs are disabled. All inputs are

ignored when nSLEEP is active low. When

waking up from sleep mode, approximately 1ms

of time must pass before issuing a STEP

command to allow the internal circuitry to

stabilize.

nENBL is used to control the output drivers.

When nENBL is low, the output H-bridge

outputs are enabled, and rising edges on STEP

are recognized. When nENBL is high, the H-

bridge outputs are disabled, and the STEP

input is ignored.

Blanking Time

There is usually a current spike during the

switching transition due to the

body diode’s

reverse-recovery

current

or

the

distributed

inductance or capacitance. This current spike

requires filtering to prevent it from shutting

down the high-side MOSFET erroneously. An

output of the current sense comparator when

the outputs are switched, which is also the

minimum on time for high-side MOSFET.

In automatic decay mode, if the current limit is

reached within the blanking time, the mixed

decay with 30% fast decay ratio is performed

after the blanking time.

Charge Pump

The MP6520 integrates an internal charge

pump to generate gate drive voltage for the

high-side

MOSFETs.

The

charge

pump

requires a 100nF ceramic capacitor rated for at

least the voltage applied to VIN to be connected

between the CPA and CPB, and a 1µF, 16V

ceramic capacitor connected between VCP and

VIN.