ISL6752

FN9181 Rev 4.00

Page 13 of 18

August 1, 2016

current feedback signal using Equation 13.

Next, determine the effect of the magnetizing current from

Equation 18.

CTBUF to CS.

This discussion determines the minimum external ramp that is

required. Additional slope compensation may be considered for

design margin.

If the application requires dead time of less than about 500ns,

the CTBUF signal may not perform adequately for slope

compensation. CTBUF lags the CT sawtooth waveform by 300ns

to 400ns. This behavior results in a non-zero value of CTBUF

when the next half-cycle begins when the dead time is short.

Under these situations, slope compensation may be added by

externally buffering the CT signal as shown in Figure 10.

Using CT to provide slope compensation instead of CTBUF

requires the same calculations, except that Equations 20 and 21

require modification. Equation 20 becomes:

and Equation 21 becomes:

The buffer transistor used to create the external ramp from CT

should have a sufficiently high gain (>200) so as to minimize the

required base current. Whatever base current is required reduces

the charging current into CT and will reduce the oscillator

frequency.

ZVS Full-Bridge Operation

The ISL6752 is a full-bridge zero-voltage switching (ZVS) PWM

controller that behaves much like a traditional hard switched

topology controller. Rather than drive the diagonal bridge

switches simultaneously, the upper switches (OUTUL, OUTUR) are

driven at a fixed 50% duty cycle and the lower switches (OUTLL,

OUTLR) are pulse width modulated on the trailing edge.

To understand how the ZVS method operates, one must include

the parasitic elements of the circuit and examine a full switching

cycle.

Figure 12, the power semiconductor switches have been

replaced by ideal switch elements with parallel diodes and

capacitance, the output rectifiers are ideal, and the transformer

leakage inductance has been included as a discrete element.

The parasitic capacitance has been lumped together as switch

capacitance, but represents all parasitic capacitance in the

circuit including winding capacitance. Each switch is designated

by its position; Upper Left (UL), Upper Right (UR), Lower Left (LL),

and Lower Right (LR). The beginning of the cycle, shown in

FIGURE 10. ADDING SLOPE COMPENSATION USING CT

CT

CT

CS

1

2

4

3

5

6

7

8

ISL6752

VREF

–



+

---------------------

=

V

(EQ. 23)

FIGURE 11. BRIDGE DRIVE SIGNAL TIMING

+

–

 R

6



–

------------------------------------------------------------

=



(EQ. 24)

CT

DEAD TIME

OUTLL

OUTLR

OUTUR

OUTUL

RESDEL

WINDOW

RESONANT

DELAY

PWM

PWM

PWM

PWM

FIGURE 12. IDEALIZED FULL-BRIDGE

VIN+

VIN-

UL

LL

UR

LR

VOUT+

RTN

D2

D1