ISL8121IRZ datasheet(10/26 Pages) RENESAS

10 / 26 page

ISL8121

FN6352 Rev 2.00

Page 10 of 26

October 27, 2009

has a combined ripple frequency twice the frequency of

one of its phases. In addition, the peak-to-peak

amplitude of the combined inductor currents is

proportionately reduced. Increased ripple frequency and

lower ripple amplitude generally translate to lower per-

channel inductance and/or lower total output capacitance

for any given set of performance specification.

Figure 3 illustrates the additive effect on output ripple

frequency. The two channel currents (IL1 and IL2),

combine to form the AC ripple current and the DC load

current. The ripple component has two times the ripple

frequency of each individual channel current.

To understand the reduction of ripple current amplitude

in the multi-phase circuit, examine Equation 3, which

represents an individual channel’s peak-to-peak inductor

current.

VIN and VOUT are the input and output voltages,

respectively, L is the single-channel inductor value, and

fS is the switching frequency.

The output capacitors conduct the ripple component of

the inductor current. In the case of multi-phase

converters, the capacitor current is the sum of the ripple

currents from each of the individual channels.

Peak-to-peak ripple current decreases by an amount

proportional to the number of channels. Output-voltage

ripple is a function of capacitance, capacitor equivalent

series resistance (ESR), and inductor ripple current.

Reducing the inductor ripple current allows the designer

to use fewer or less costly output capacitors (should

output high-frequency ripple be an important design

parameter).

Another benefit of interleaving is the reduction of input

ripple current. Input capacitance is determined in a large

part by the maximum input ripple current. Multi-phase

topologies can improve overall system cost and size by

lowering input ripple current and allowing the designer to

reduce the cost of input capacitance. The example in

Figure 4 illustrates input currents from a two-phase

converter combining to reduce the total input ripple

current.

Figure 28, part of “Input Capacitor Selection” on

page 24, can be used to determine the input-capacitor

RMS current based on load current and duty cycle. The

figure is provided as an aid in determining the optimal

input capacitor solution.

PWM OPERATION

One switching cycle for the ISL8121 is defined as the

time between consecutive PWM pulse terminations (turn-

off of the upper MOSFET on a channel). Each cycle begins

when a switching clock signal commands the upper

MOSFET to go off. The other channel’s upper MOSFET

conduction is terminated 1/2 of a cycle later.

Once a channel’s upper MOSFET is turned off, the lower

MOSFET remains on for a minimum of 1/3 cycle. This

forced off time is required to assure an accurate current

sample. Following the 1/3-cycle forced off time, the

controller enables the upper MOSFET output. Once

enabled, the upper MOSFET output transitions high when

the sawtooth signal crosses the adjusted error-amplifier

output signal, as illustrated in Figure 2. Just prior to the

upper drive turning the MOSFET on, the lower MOSFET

drive turns the freewheeling element off. The upper

MOSFET is kept on until the clock signals the beginning of

the next switching cycle and the PWM pulse is

terminated.

FIGURE 3. PWM AND INDUCTOR-CURRENT

WAVEFORMS FOR 2-PHASE CONVERTER

PWM2

PWM1

IL2

IL1

IL1 + IL2

ILPP



VIN VOUT

–

 V

OUT



LfS V



----------------------------------------------------------

(EQ. 3)

IPP

VIN NVOUT



–

 V

OUT



LfS V



--------------------------------------------------------------------

(EQ. 4)

FIGURE 4. INPUT CAPACITOR CURRENT AND

INDIVIDUAL CHANNEL CURRENTS IN A

2-PHASE CONVERTER

Q1 D-S CURRENT

Q3 D-S CURRENT

CIN CURRENT

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