HIP6013CBZ datasheet(6/11 Pages) RENESAS

6 / 11 page

HIP6013

FN4325 Rev 1.00

Page 6 of 11

November 3, 2005

The over-current function will trip at a peak inductor current

(IPEAK) determined by:

where IOCSET is the internal OCSET current source (200A -

typical). The OC trip point varies mainly due to the MOSFET’s

rDS(ON) variations. To avoid over-current tripping in the normal

operating load range, find the ROCSET resistor from the

equation above with:

1. The maximum rDS(ON) at the highest junction temperature.

2. The minimum IOCSET from the specification table.

3. Determine

where

I is the output inductor ripple current.

For an equation for the ripple current see the section under

component guidelines titled ‘Output Inductor Selection’.

A small ceramic capacitor should be placed in parallel with

ROCSET to smooth the voltage across ROCSET in the

presence of switching noise on the input voltage.

Application Guidelines

Layout Considerations

As in any high frequency switching converter, layout is very

important. Switching current from one power device to another

can generate voltage transients across the impedances of the

interconnecting bond wires and circuit traces. These

interconnecting impedances should be minimized by using wide,

short printed circuit traces. The critical components should be

located as close together as possible using ground plane

construction or single point grounding.

Figure 5 shows the critical power components of the converter.

To minimize the voltage overshoot the interconnecting wires

indicated by heavy lines should be part of ground or power

plane in a printed circuit board. The components shown in

Figure 6 should be located as close together as possible.

Please note that the capacitors CIN and CO each represent

numerous physical capacitors. Locate the HIP6013 within 3

inches of the MOSFETs, Q1. The circuit traces for the

MOSFETs’ gate and source connections from the HIP6013

must be sized to handle up to 1A peak current.

Figure 6 shows the circuit traces that require additional layout

consideration. Use single point and ground plane construction

for the circuits shown. Minimize any leakage current paths on

the SS PIN and locate the capacitor, Css close to the SS pin

because the internal current source is only 10

A. Provide local

VCC decoupling between VCC and GND pins. Locate the

capacitor, CBOOT as close as practical to the BOOT and

PHASE pins.

TIME (20ms/DIV)

10A

15A

FIGURE 4. OVER-CURRENT OPERATION

IPEAK

IOCSET ROCSET



rDS ON



---------------------------------------------------

IPEAK for IPEAK IOUT MAX



I

 2





FIGURE 5. PRINTED CIRCUIT BOARD

POWER AND GROUND PLANES OR ISLANDS

UGATE

PHASE

VIN

VOUT

RETURN

HIP6013

CIN

+12V

HIP6013

GND

VCC

BOOT

VOUT

PHASE

FIGURE 6. PRINTED CIRCUIT BOARD

SMALL SIGNAL LAYOUT GUIDELINES

+VIN

CBOOT

CVCC

CSS

HIP6013CBZ Datasheet(PDF) 6 Page - Renesas Technology Corp

HIP6013CBZ Datasheet(HTML) 6 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11

Datasheet Download

Link URL