HIP6013

FN4325 Rev 1.00

Page 7 of 11

November 3, 2005

Feedback Compensation

Figure 7 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

(Vout) is regulated to the Reference voltage level. The error

oscillator (OSC) triangular wave to provide a pulse-width

modulated (PWM) wave with an amplitude of Vin at the

PHASE node. The PWM wave is smoothed by the output

filter (Lo and Co).

The modulator transfer function is the small-signal transfer

Gain and the output filter (Lo and Co), with a double pole

the modulator is simply the input voltage (Vin) divided by the

peak-to-peak oscillator voltage

Modulator Break Frequency Equations

The compensation network consists of the error amplifier

a closed loop transfer function with the highest 0dB crossing

 The equations below relate the compensation

network’s poles, zeros and gain to the components (R1, R2,

R3, C1, C2, and C3) in Figure 8. Use these guidelines for

locating the poles and zeros of the compensation network:

Compensation Break Frequency Equations

1. Pick Gain (R2/R1) for desired converter bandwidth

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

Figure 8 shows an asymptotic plot of the DC-DC converter’s

gain vs frequency. The actual Modulator Gain has a high

gain peak do to the high Q factor of the output filter and is

not shown in Figure 8. Using the above guidelines should

give a Compensation Gain similar to the curve plotted. The

open loop error amplifier gain bounds the compensation

capabilities of the error amplifier. The Closed Loop Gain is

constructed on the log-log graph of Figure 8 by adding the

Modulator Gain (in dB) to the Compensation Gain (in dB).

This is equivalent to multiplying the modulator transfer

function to the compensation transfer function and plotting

the gain.

The compensation gain uses external impedance networks

overall loop. A stable control loop has a gain crossing with

Include worst case component variations when determining

phase margin.

FIGURE 7. VOLTAGE - MODE BUCK CONVERTER

COMPENSATION DESIGN

OSC

REFERENCE

ESR

ERROR

AMP

PWM

DRIVER

(PARASITIC)

-

REF

R1

R3

R2

C3

C2

C1

COMP

FB

HIP6013

COMPARATOR

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

+

-

+

-

+

1

2







---------------------------------------

1

2









--------------------------------------------

1

2

 R2 C1





---------------------------------

1

2

 R2



C1 C2



C1 + C2

----------------------







------------------------------------------------------

1

2



R1 + R3





C3



-----------------------------------------------------

1

2

 R3



C3



---------------------------------