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ISL97635IRZ Datasheet(PDF) 7 Page - Renesas Technology Corp |
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ISL97635IRZ Datasheet(HTML) 7 Page - Renesas Technology Corp |
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7 / 28 page  ISL97635 FN6434 Rev.3.00 Page 7 of 28 Sep 26, 2017 Stop Condition Setup Time tSU:STO 4.0 µs Data Hold Time tHD:DAT 300 ns Data Setup Time tSU:DAT 250 ns Clock Low Period tLOW 4.7 µs Clock High Period tHIGH 4.0 50 µs Clock/data Fall Time tF 300 ns Clock/data Rise Time tR 1000 ns GENERAL TIMING SPECIFICATIONS (Note 7) Minimum Setup Time Between VIN Rising above VUVLO with EN = 1 and SMBus Communications t1 EN = 1, TA = +25°C, VDC capacitor < 10µF 80 µs Minimum Setup Time Between EN Going High with VIN above VUVLO and SMBus Communications t2 VIN > VUVLO, TA= +25°C, VDC capacitor < 10µF 80 µs Minimum Time Between VIN Rising above VUVLO with EN = 1 to SMBus BL CTRL On t3 EN = 1, TA = +25°C 4.5 ms Minimum Time Between EN Going High with VIN above VUVLO to SMBus BL CTRL On t4 VIN > VUVLO, TA = +25°C 4.5 ms Minimum Time for LED Output to Respond to SMBus Data at any Levels t5 VIN > VUVLO, EN = 1, TA = +25°C 5µs Response Time Between Backlight CTRL Off with Boost Not Switching to Backlight CTRL On with Boost Switching t6 VIN > VUVLO, EN = 1, TA = +25°C 5µs Response Time Between Backlight CTRL On with Boost Switching to Backlight CTRL Off with Boost Not Switching t7 VIN > VUVLO, EN = 1, TA = +25°C 5µs LED Channel Short-Circuit Fault Detection to Status Register Data Ready t8 VIN > VUVLO, EN = 1, TA = +25°C, LEDs Active 6ms VOUT-GND Short-Circuit Detection During Operation to Status Register Data Ready t9 VIN > VUVLO, EN = 1, TA = +25°C, Fault FET used 5µs Time Between VIN Rising Above VUVLO with EN = 1 and VOUT-GND Short being Reported in Status Register t10 EN = 1, VDC capacitor < 10µF, TA = +25°C, Fault FET used. 30 ms Time Between EN Going High with VIN Above VUVLO and a VOUT-GND Short being Reported in Status Register t11 VIN > VUVLO, VDC capacitor < 10µF, TA = +25°C, Fault FET used. 30 ms CURRENT SOURCES Dominant Channel Current Source Headroom at IIN Pin VHEADROOM ILED = 20mA, TA = +25°C 100 (Note 8) mV Dominant Channel Current Sink Headroom Range at IIN Pin VHEADROOM_RANGE ILED = 20mA, TA = +25°C 10 mV Voltage at RSET Pin VRSET RSET = 36.6kΩ 680 700 720 mV Maximum LED Current per Channel ILEDmax RSET = 20.9kΩ 35 mA PWM GENERATOR Generated PWM Frequency FPWM CFPWM = 27nF CPWMO = 220nF 200 Hz Duty Cycle Of Generated PWM (DC-to-PWM) DPWM VPWMO = 0.3V CFPWM = 27nF 90 % VPWMO = 1.1V CFPWM = 27nF 10 % Electrical Specifications All specifications below are tested at T A = -40°C to +85°C; VIN = 12V, EN = 5V, RSET = 36.6kΩ, unless otherwise noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYMBOL CONDITION MIN TYP MAX UNIT |
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