AD8315ARMZ datasheet(17/22 Pages) AD

17 / 22 page

Data Sheet

AD8315

Rev. D | Page 17 of 22

This bandwidth is highest at the point where the slope of the

tangent drawn on this curve is greatest, that is, for power outputs

near the center of the PA range, and is much reduced at both

the minimum and the maximum power levels, where the slope

of the gain control curve is lowest due to the S-shaped form.

Using smaller values of CFLT, the loop bandwidth generally

increases in inverse proportion to the value. Eventually, however, a

secondary effect appears due to the inherent phase lag in the power

amplifier control path, some of which can be due to parasitic or

deliberately added capacitance at the VAPC pin. This results in

the characteristic poles in the ac loop equation moving off the

real axis and thus becoming complex (and somewhat resonant).

This is a classic aspect of control loop design. The lowest

permissible value of CFLT must be determined experimentally for a

particular amplifier. For GSM and DCS power amplifiers, CFLT

typically ranges from 150 pF to 300 pF.

In many cases, some improvement in the worst-case response

time can be achieved by including a small resistance in series

with CFLT; this generates an additional 0 in the closed-loop transfer

function, that serves to cancel some of the higher order poles in

the overall loop. A combination of main capacitor CFLT shunted

by a second capacitor and resistor in series is also useful in

minimizing the settling time of the loop.

NC = NO CONNECT

RFIN

ENBL

VSET

VPOS

VAPC

COMM

FLTR

ENABLE

0V/2.7V

LDC15D190A0007A

ATTN

20dB

PF08107B

VCTL

VAPC

1000pF

3.5V

1000pF

0.1µF

1.5kΩ

150pF

52.3Ω

49.9Ω

4.7µF

500Ω

AD8315

BAND

SELECT

0V/2V

POUT GSM

35dBm MAX

POUT DCS

32dBm MAX

PIN GSM

3dBm

PIN DCS

3dBm

(OPTIONAL,

SEE TEXT)

+VS

2.7V

R31

1kΩ

R21

600Ω

1R2, R3 OPTIONAL,

SEE TEXT

8-BIT

RAMP DAC

0V TO 2.55V

ANTENNA

Figure 39. Dual-Mode (GSM/DCS) PA Control Example

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