AD8315ARMZ datasheet(18/22 Pages) AD

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AD8315

Data Sheet

Rev. D | Page 18 of 22

MOBILE HANDSET POWER CONTROL EXAMPLE

Figure 39 shows a complete power amplifier control circuit for a

dual-mode handset. The PF08107B (Hitachi), a dual mode

(GSM, DCS) PA, is driven by a nominal power level of 3 dBm.

The PA has a single gain control line; the band to be used is

selected by applying either 0 V or 2 V to the PA VCTL input.

Some of the output power from the PA is coupled off using a

dual-band directional coupler (Murata LDC15D190A0007A).

This has a coupling factor of approximately 19 dB for the GSM

band and 14 dB for DCS and an insertion loss of 0.38 dB and

0.45 dB, respectively. Because the PF08107B transmits a maximum

power level of 35 dBm for GSM and 32 dBm for DCS, additional

attenuation of 20 dB is required before the coupled signal is

applied to the AD8315. This results in peak input levels to the

AD8315 of −4 dBm (GSM) and −2 dBm (DCS). While the

AD8315 gives a linear response for input levels up to 2 dBm,

for highly temperature-stable performance at maximum PA

output power, the maximum input level must be limited to

approximately −2 dBm (see Figure 6 and Figure 8). This does,

however, reduce the sensitivity of the circuit at the low end.

The operational setpoint voltage, in the range 250 mV to 1.4 V,

is applied to the VSET pin of the AD8315. This is typically supplied

by a DAC. The AD8315 VAPC output drives the level control

pin of the power amplifier directly. VAPC reaches a maximum

value of approximately 2.5 V on a 2.7 V supply while delivering

the 3 mA required by the level control input of the PA. This is

more than sufficient to exercise the gain control range of the PA.

During initialization and completion of the transmit sequence,

VAPC must be held at the minimum level of 250 mV by keeping

VSET below 200 mV.

In this example, VSET is supplied by an 8-bit DAC that has an

output range from 0 V to 2.55 V or 10 mV per bit. This sets the

control resolution of VSET to 0.4 dB/bit (0.04 dB/mV times

10 mV). If finer resolution is required, the DAC output voltage

can be scaled using two resistors, as shown in Figure 39. This

converts the DAC maximum voltage of 2.55 V down to 1.6 V

and increases the control resolution to 0.25 dB/bit.

A filter capacitor (CFLT) must stabilize the loop. The choice of CFLT

depends to a large degree on the gain control dynamics of the

power amplifier, something that is frequently poorly characterized,

so some trial and error can be necessary.

In this example, a 150 pF capacitor is used and a 1.5 kΩ series

resistor is included. This adds a zero to the control loop and

increases the phase margin, which helps to make the step response

of the circuit more stable when the PA output power is low and

the slope of the PA power control function is the steepest.

A smaller filter capacitor can be used by inserting a series

resistor between VAPC and the control input of the PA. A

series resistor works with the input impedance of the PA to

create a resistor divider and reduces the loop gain. The size of

the resistor divider ratio depends upon the available output

swing of VAPC and the required control voltage on the PA.

This technique can also be used to limit the control voltage in

situations where the PA cannot deliver the power level being

demanded by VAPC. Overdrive of the control input of some

PAs causes increased distortion. It must be noted, however, that

if the control loop opens (that is, VAPC goes to the maximum

value in an effort to balance the loop), the quiescent current of

the AD8315 increases somewhat, particularly at supply voltages

greater than 3 V.

Figure 40 shows the relationship between VSET and output

power (POUT) at 0.9 GHz . The overall gain control function is

linear in dB for a dynamic range of over 40 dB. Note that for

VSET voltages below 300 mV, the output power drops off steeply

as VAPC drops toward the minimum level of 250 mV.

–10

–20

–30

–40

–1

–2

–3

–4

1.6

+85°C

+25°C

–30°C

+85°C

+25°C

–30°C

VSET (V)

0.2

0.4

0.6

0.8

1.0

1.2

1.4

Figure 40. POUT vs. VSET at 0.9 GHz for Dual-Mode Handset

Power Amplifier Application, −30°C, +25°C, and +85°C

ENABLE AND POWER-ON

The AD8315 can be disabled by pulling the ENBL pin to

ground. This reduces the supply current from the nominal level

of 7.4 mA to 4 μA. The logic threshold for turning on the device

is at 1.5 V with 2.7 V supply voltage. A plot of the enable glitch

is shown in Figure 23. Alternatively, the device can be completely

disabled by pulling the supply voltage to ground. To minimize

glitch in this mode, ENBL and VPOS must be tied together. If

VPOS is applied before the device is enabled, a narrow 750 mV

glitch results (see Figure 30).

In both situations, the voltage on VSET must be kept below

200 mV during power-on and power-off to prevent any unwanted

transients on VAPC.

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