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Datasheet

Datasheet

BD62012FS

TSZ02201-0828ABB00020-1-2

© 2013 ROHM Co., Ltd. All rights reserved.

15.MAR.2013 Rev.003

http://www.rohm.com

TSZ22111 · 15 · 001

11) Thermal shutdown (TSD) circuit

The TSD circuit operates when the junction temperature of the controller exceeds the preset temperature (175°C

nominal). At this time, the controller forces all driver outputs low. Since thermal hysteresis is provided in the TSD circuit,

the chip returns to normal operation when the junction temperature falls below the preset temperature (150°C nominal).

The TSD circuit is designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or

guarantee its operation in the presence of extreme heat. Do not continue to use the IC after the TSD circuit is activated,

and do not use the IC in an environment where activation of the circuit is assumed.

12) Motor lock protection (MLP) circuit

When the controller detects the motor locking during fixed time of 4 seconds nominal when each edge of the hall signal

doesn't input either, the controller forces all driver outputs low under a fixed time 20 seconds nominal, and self-returns to

that the motor cannot start up when the controller doesn’t detect the motor rotation by the minimum duty control.

13) External fault signal input pin (FIB pin, low active)

The FIB pin can force all controller driver outputs low at any time. The FIB pin is pulled up to VREG internally by a 100

k

Ω resistor. Therefore, an open drain output can be connected directly. It is recommended to pull up FIB pin to VREG

voltage when this function is not used or malfunctioning because of the noise.

14) Hall signal wrong input detection

Hall element abnormalities may cause incorrect inputs that vary from the normal logic. When all hall input signals go high

or low, the hall signal wrong input detection circuit forces all driver outputs low. And when the controller detects the

abnormal hall signals continuously for four times or more motor rotation, the controller forces all driver outputs low and

latches the state. It is released if the duty control voltage VSP is forced to ground level once.

15) Internal voltage regulator

The internal voltage regulator VREG is output for the bias of the hall

element and the phase control setting. However, when using the VREG

ground in order to stabilize output, a value of 1 µF or more should be used.

In this case, be sure to confirm that there is no oscillation in the output.

Figure 6. VREG output pin application example

HUP

HUN

HVP

HVN

HWP

HWN

HU

HV

HW

VCC

Controller IC

R1

VREG