SSM3582BCPZ datasheet(32/59 Pages) AD

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SSM3582

Data Sheet

Rev. 0| Page 32 of 59

Table 20. Fault Reporting Registers

Fault Type

Flag Set Condition

Status Reported Register

PVDD Undervoltage (UV)

PVDD below <3.6 V

5 V Regulator UV

5 V regulator voltage at AVDD < 3.6 V

Limiter/Gain Reduction Engage

Left channel limiter engaged

Right channel limiter engaged

Clipping, Left Channel

Left channel DAC clipping

Clipping, Right Channel

Right channel DAC clipping

Output Overcurrent (OC)

Left channel output current > 6 A peak

Right channel output current > 6 A peak

Die Overtemperature (OT)

Die temperature > 145°C

Die Overtemperature Warning (OTW)

Die temperature > 117°C

Battery Voltage > VBAT_INF_x

Battery voltage PVDD > VBAT_INF_L

Battery voltage PVDD > VBAT_INF_R

FAULTS AND LIMITER STATUS REPORTING

The SSM3582 offers comprehensive protections against the

faults at the outputs and reporting to help with system design.

The faults listed in Table 20 are reported using the status registers.

The faults listed in Table 20 are reported in Register 0x18 and

the system.

In the event of a fault occurrence, use Register 0x0B to control

how the device reacts to the faults.

Table 21. Register 0x16, Register 0x17, Fault Recovery

Fault Type

Flag Set Condition

Status Reported

OTW

The amount of gain

reduction applied if there

is an OTW for left channel

Bits[1:0], OTW_

GAIN_L

The amount of gain

reduction applied if there

is an OTW for the right

channel

Bits[5:4], OTW_

GAIN_R

Manual

Recovery

Use to attempt manual

recovery in case of a fault

event

Bit 7, MRCV

Autorecovery

Attempts

When autorecovery from

faults is used, set the

number of attempts using

this bit

Bits[5:4], MAX_AR

Recovery can be automatic

or manual

Bit 2, ARCV_UV

Die OT

Recovery can be automatic

or manual

Bit 1, ARCV_OT

Recovery can be automatic

or manual

Bit 0, ARCV_OC

When the automatic recovery mode is set, the device attempts

to recover itself after the fault event and, in case the fault

persists, then the device sets the fault again. This process

repeats until the fault is resolved.

When the manual recovery mode is used, the device shuts down

and the recovery must be attempted using the system micro-

controller.

VBAT (PVDD) SENSING

The SSM3582 contains an 8-bit ADC that measures the voltage

of the battery voltage (VBAT/PVDD) supply. The battery voltage

information is stored in Register 0x1A as an 8-bit unsigned

format. The ADC input range is fixed internally at 3.8 V to

16.2 V. To convert the hexadecimal value to the voltage value,

use the following steps:

Convert the hexadecimal value to decimal. For example, if the

hexadecimal value is 0xA9, the decimal value is 169.

Calculate the voltage using the following equation:

Voltage = 3.8 V + 12.4 V × Decimal Value/255

With a decimal value of 169,

Voltage = 3.8 V + 12.4 V × 169/255 = 12.02 V

LIMITER AND BATTERY TRACKING THRESHOLD

CONTROL

The SSM3582 contains an output limiter that can be used to

limit the peak output voltage of the amplifier. The limiter works

on the rms and peak value of the signal. The limiter threshold,

slope, attack rate, and release rate are programmable using

channel and Register 0x11, Register 0x12, Register 0x13 for the

right channel. The limiter can be enabled or disabled using

LIM_EN_L, Bits[1:0] in Register 0x0E, Bits[1:0] for the left

channel and the LIM_EN_R bits, Bits[1:0] in Register 0x11, for

the right channel.

The threshold at which the output is limited is determined by

the LIM_THRES_L bits setting, Bits[7:3] in Register 0x0F for

the left channel, and the LIM_THRES_R bits setting, Bits[7:3]

in Register 0x12 for the right channel. When the ouput signal

level exceeds the set threshold level, the limiter activates and

limits the signal level to the set limit. Below the set threshold,

the output level is not affected.

SSM3582BCPZ Datasheet(PDF) 32 Page - Analog Devices

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