CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

15

POST OFFICE BOX 655303

APPLICATION INFORMATION

IN

CLK

IN

CDCM1802

VBB

Figure 15. Typical Application Setting for Single-Ended Input Signals Driving the CDCM1802

device behavior during RESET and control pin switching

output behavior when enabling the device (EN = 0 % 1)

In disable mode (EN = 0), all output drivers are switched in high-Z mode. The bandgap, current references, the

amplifier, and the S0 and S1 control inputs are also switched off. In the same mode, all flip-flops will be reset.

The typical current consumption is likely below 500 µA (to be measured).

When the device will be enabled again it takes maximal 1 µs for the settling of the reference voltage and currents.

During this time the output Y0 and Y0 drive a high signal. Y1 is unknown (could be high or low). After the settle

time, the outputs go into the low state. Due to the synchronization of each output driver signal with the input

clock, the state of the waveforms after enabling the device look like those shown in Figure 16. The inverting input

and output signal is not included. The Y:/1 waveform is the undivided output driver state.