Copyright

© ANPEC Electronics Corp.

Rev. A.3 - Jun., 2017

APL6002

www.anpec.com.tw

11

Function Description (Cont.)

Alert Flag

The Alert Flag is used to indicate the system state.

When the setting condition is established at the AINx

voltage, the APL6002 will make the internal MOS in the

Alert pin turns on and pull low 50us every 2s cycle time.

Alert

Control

Logic

VDD

Alert

Alert Threshold Level Setting

AIN1 Alert level set-up (TL1): Reg0x00[7] (MSB) ~ Reg0x00[0] (LSB)

AIN2 Alert level set-up (TL2): Reg0x01[7] (MSB) ~ Reg0x01[0] (LSB)

AIN3 Alert level set-up (TL3): Reg0x02[7] (MSB) ~ Reg0x02[0] (LSB)

If one of conditions is established include TL1>TD1, TL2>TD2 or TL3>TD3, the Alert function will be enabled, and the

Alert Indication of internal resistor Reg0x06[6:4] will be set to 1 that shows as below:

If the Reg0x00 (TL1) > Reg0x03 (TD1), than the bit Reg0x06[4] = 1, else the bit Reg0x06[4] = 0

If the Reg0x01 (TL2) > Reg0x04 (TD2), than the bit Reg0x06[5] = 1, else the bit Reg0x06[5] = 0

If the Reg0x02 (TL3) > Reg0x05 (TD3), than the bit Reg0x06[6] = 1, else the bit Reg0x06[6] = 0

Chip ID: Reg0xB2[7:0] = 0x1A

Bi ts

Re gister

Add ress

Re gister

Na me

D7

D6

D5

D4

D3

D2

D1

D0

Re ad/

Write

De fa ult

Value

0x00

TL1

TL 1[7:0 ]

R/W

00h

0x01

TL2

TL 2[7:0 ]

R/W

00h

0x02

TL3

TL 3[7:0 ]

R/W

00h

0x03

TD1

TD1 [7:0]

R

00h

0x04

TD2

TD2 [7:0]

R

00h

0x05

TD3

TD3 [7:0]

R

00h

0x06

ALT

Re ve rsed

A M3

AM2

AM1

Reversed

R

00h

0xB 2

Chi p ID

Chip ID = 0 x1A

R

1A h