ADV7481WBBCZ datasheet(19/22 Pages) AD

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Data Sheet

ADV7481

COMPONENT PROCESSOR

The ADV7481 has one any-to-any 3 × 3 CSC matrix. The CSC

block is located in the processing path before the CP section.

CSC enables YCbCr-to-RGB and RGB-to-YCbCr conversions.

Many other standards of color space can be implemented using

the color space converter.

CP features include

•

Support for all video modes supported by the HDMI/MHL

receiver. These include 525i, 625i, 525p, 625p, 1080i, 1080p,

and display resolutions from VGA (640 × 480 at 60 Hz) to

UXGA (1600 × 1200 at 60 Hz).

•

Manual adjustments including gain (contrast), offset

(brightness), hue, and saturation.

•

Free run output mode that provides stable timing when no

video input is present.

•

Timing adjustments controls for HS/VS/DE timing.

ANALOG FRONT END

The ADV7481 AFE comprises a single high speed, 10-bit ADC

that digitizes the analog video signal before applying it to the

SDP. The AFE uses differential channels to the ADC to ensure

high performance in mixed-signal applications and to enable

differential CVBS to be connected directly to the ADV7481.

Up to eight analog inputs can be connected to the AFE. The

front end also includes an 8-channel input mux that enables

different configurations of single-ended CVBS (up to eight),

pseudo differential or fully differential CVBS (up to four), Y/C

(up to four), and YPbPr (up to two) analog inputs.

Current clamps are positioned in front of the ADC to ensure

that the video signal remains within the range of the converter.

A resistor divider network is required before each analog input

channel to ensure that the input signal is within the range of the

ADC. Figure 14 shows a typical voltage divider network for

single-ended inputs, Figure 15 shows a typical voltage divider

network for pseudo differential inputs, and Figure 16 shows a

typical voltage divider network for fully differential inputs. The

choice of the resistor divider shown in Figure 16 provides a

common-mode range of up to 4 V in fully differential CVBS

input mode. Fine clamping of the video signal is performed

downstream by digital fine clamping within the ADV7481.

Figure 14. Typical Single-Ended Input Voltage Divider Network

Figure 15. Typical Pseudo Differential Input Resistor Divider Network

Figure 16. Typical Fully Differential Input Resistor Divider Network

The ADC features three clocking rates that allow 4×

oversampling per channel for CVBS mode, Y/C mode, and

YPbPr mode.

The fully differential AFE of the ADV7481 provides inherent

small and large signal noise rejection, improved electro-

magnetic interference (EMI) protection, and the ability to

absorb ground bounce. Support is provided for both true

differential and pseudo differential signals.

The main AFE features include

•

A single 172 MHz, 10-bit ADC that enables true 8-bit

video decoding.

•

8-channel analog input mux that enables multiple source

connections without the requirement of an external mux.

•

A current clamp control loop that ensures that any dc

offsets are removed from the video signal entering the SDP.

•

Diagnostic capability on all differential inputs.

•

Support for 4 V common-mode input range.

•

Support for analog input signals up to 1 V p-p.

•

Support for single-ended, pseudo differential, and fully

differential inputs.

SHORT TO BATTERY DIAGNOSTICS

In differential mode, the ADV7481 is protected against STB

events by ac coupling capacitors (see Figure 15 and Figure 16).

The input network resistors are sized to reduce the current flow

during an STB event, thus preventing damage to the resistors.

Note that the input network resistors and the ac coupling

capacitors must be chosen with ratings guaranteeing they are

able to withstand the high voltage of STB events.

The four diagnostic inputs of the ADV7481 provide diagnostic

capability for all differential inputs. The ADV7481 can detect an

STB event on either the positive or the negative composite input

and trigger an interrupt. The 75 Ω (pseudo differential) or 150 Ω

(fully differential) parallel termination resistor enables one

AIN

ANALOG

INPUT

51Ω

24Ω

100nF

AINx

AINy

ANALOG INPUT

CVBS_P

CVBS_N

1.3kΩ

75Ω

430Ω

100nF

AINx

AINy

ANALOG INPUT

CVBS_P

CVBS_N

1.3kΩ

150Ω

430Ω

100nF

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